Seungchul Jung

Robust and efficient synchronous buck converter with near-optimal dead-time control

In switching power converters, the turn on/off process of switches is crucial for the reliability and efficiency of the converter. In general, optimum switching is challenging, and it is particularly difficult for hard switching. The MOSFET synchronous buck converter having wide applications due to high switching speed and low loss, however, operates in hard switching and needs a good timing control for its switching. On/off commutation dead-times should be adjusted carefully in accordance with load current change. Previous work on the dead-time control includes predictive gate drive technique [1], load current sensing [2][7], sensor-less optimization technique [3], and delay-locked loops [4–6]. These techniques have problems of sensing noisy switching node [1, 4–6] or load current [2, 7], and requiring high quantizing resolution [3]. In this paper, a near optimum dead-time control method is proposed thate resolves such problems.

Accurate Dead-Time Control for Synchronous Buck Converter With Fast Error Sensing Circuits

Dead-time controls for synchronous buck converter are challenging due to the difficulties in accurate sensing and processing the on/off dead-time errors. For the control of dead-times, an integral feedback control using switched capacitors and a fast timing sensing circuit composed of MOSFET differential amplifiers and switched current sources are proposed. Experiments for a 3.3 V input, 1.5 V-0.3 A output converter demonstrated 1.3 ~ 4.6% efficiency improvement over a wide load current range.

A Direct-Type Fast Feedback Current Driver for Medium-to Large-Size AMOLED Displays

The current or voltage driving schemes are employed for pulse-amplitude modulation (PAM) in AMOLED displays. Current driving methods have advantages over voltage driving schemes including improvement of luminance uniformity at display panels and compensation of TFT characteristics at pixels. degrade the driving accuracy. This paper introduces a direct-type fast feedback current (DFFC) driver that offers fast settling time with good accuracy by comparing the data with the pixel current directly. An optimum compensation method for the feedback loop is suggested as well.

PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.

A novel readout IC with high noise immunity for charge-based touch screen panels

The critical issues in charge-based touch screen panels for large size display are noise and speed. To solve these, this paper introduces a two-point relative sensing based ‘Delta-Integration’ scheme. It eliminates local noise and increases a readout difference between the touched and non-touched area. As a result, it can replace a high-resolution ADC with a comparator and counter. In addition, the single-bit conversion of Δ-integration method and the proposed wide-bandwidth charge amplifier solve a speed issue of a large display. The prototype chip is implemented in a 0.35-µm CMOS technology.

56.4: A Cascaded-Dividing Current DAC with Fine Pitch for High-Resolution AMOLED Display Drivers

An 8-bit cascaded-dividing DAC that can operate at a low power supply voltage is proposed. Occupying less than one eleventh of the chip area of a conventional binary-weighted DAC with an equivalent resolution, the proposed DAC features a low operation voltage of 2 V with a good DNL and INL of less than 0.15 LSB. The proposed DAC is expected to be adequate for current-driving AMOLED drivers that have very demanding requirements of a narrow channel pitch as well as high linearity and resolution for the data channel DACs.

P-42: A 10 bit Gray Scale Digital-to-Analog Converter with an Interpolating Buffer Amplifier for AMLCD Column Drivers

A 10 bit digital-to-analog converter (DAC) with an interpolating buffer amplifier is proposed for AMLCD column drivers. The proposed circuit is more effective than a conventional circuit in decreasing the DAC (Pass-Transistor Logic) area per channel. The average static current per channel is 1.8 μA and the average interpolating error rate in most of the gray range is a sufficiently small rate of 2.5 % (and less than 0.5 % in the mid-gray range). The uniformity of the channel output is also guaranteed by the proposed error-reduction technique.

High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)

This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components ( 1 pF and 80 kΩ in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm2 of core area (w/o power transistors) using 0.18 μm I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.

High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)

For the controller design of a DC-DC converter, a Time-Mode Miller Compensation (TMMC) is introduced in this paper. Using this concept, the consuming area of the DC-DC converter can be significantly reduced without any off-chip compensation components. The chip is implemented in 0.18μm I/O CMOS whose size is similar to 0.35μm CMOS, and the core size of this work is only 0.12mm2. Peak efficiency is 90.6%, with switching frequency of 1.15MHz.

A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process

A 65nm CMOS Low Drop-Out (LDO) Regulator is presented employing Gain Boost-Up and Differential Feed Forward Noise Cancellation (DFFNC) to maximize the Power Supply Rejection. The gain boost-up consists of both negative feedback and positive feedback in the error amplifier. With a 1.2V supply voltage, this LDO regulator has a 200mV drop-out voltage and the ability to handle a maximum 25mA load current. The measurement results show a -47dB PSR ratio up to 10MHz and 0.8% of load regulation for the full load current change.