Tafadzwa Magaya

Adhesive enabling technology for directly plating copper onto glass/ceramic substrates

This study showcases that metal oxide adhesion promoters (MOAP) can function as strong adhesive layers between plated Cu and glass/ceramic. In this new approach a 10-200 nm thick metal oxide layer is deposited by a modified sol gel process followed by sintering. This enables reliable electroless and electrolytic metallization of glass or ceramic substrates. With the new approach, Cu can be plated on a variety of glass types. Substrate roughness appears to have only limited impact. The new approach also can be extended to ceramics such as Al2O3 and BaTiO3. Cu film of over 50 μm thickness can be deposited without delamination. Adhesion of 15 μm thick Cu layers as measured by 90° peel strength tests can achieve well above 5 N/cm. The plated layer stands up well to solder reflow shock (260°C) and HAST without significant loss of adhesion. Good coverage of the MOAP layer and excellent copper adhesion inside the via holes of patterned substrates have been also demonstrated. There is no indication of blockages of holes with diameters >20 μm by the process.

VitroCoat GI - Ultra-thin adhesive layer for metallization of glass interposer

In this paper a glass-copper interface adhesion promoting thin film is described that forms chemical bonds with glass, and mechanically and possibly chemically anchors to copper to create strong, reliable adhesion between the glass substrate and the deposited metal. Wet chemical deposition of a low volatile organic content (VOC), emissions free, cost-effective, water based coating solution was used to create a thin, transparent metal oxide film that then enables electroless, and electrolytic copper plating directly onto glass. With this approach, a copper film thickness of 30μm can be applied without delamination from the smooth glass. Adhesion at 15μm Cu thickness as measured by 90° peel strength tests can achieve values of ≥4 N/cm. Thermal and stress tests using lead free reflow conditions and Highly Accelerated Stress Testing (HAST) were carried out with manageable to minimal adhesion loss. Through hole plating of aspect ratios up to 5:1 are also demonstrated. Photolithography of fine-lines as small as 5/5 μm was feasible, with very small undercut observed.

Influence of Electroless Copper on IC Reliability

The process of plating through holes (PTH) is inherent to modern PCB manufacturing. In an arena of increasing circuit density and layer counts, the reliability of the PTH process is under constant microscopic examination. The aim of electroless copper is to plate a conductive layer through a hole or into a blind microvia. In this context an interconnect (IC) refers to the copper to copper adhesion within the functional constraints of a circuit board. As these can include many inner layers, the inter connection quality is of prime concern. In addition the PTH process also inherits the issues from the preceding manufacture.

Electrolytic solder deposit for next generation flip chip solder bumping: 2010 International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) conference

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties in particular associated with achieving sufficient yields with the stencil printing process. Practical experience of current production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. Also the increased costs associated with low yields are an ever present factor. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 jim. The electrolytic deposition of tin requires an electrical connection to each surface for metal deposition; this process is shown as made using an appropriate copper seed layer which is produced onto the structured soldermask. Specially modified activation and electroless copper processes are introduced for this critical process step. Following this the use of a photo sensitive plating resist defines the SRO which is then filled with the electrolytic tin deposit. The associated processes required both for seed layer production and for removal of plating resist and subsequent etching of the seed layer are described and first qualification results are shown from the complete process. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy system and also pure tin bumping are presented together with comparison of the advantages and disadvantages. This newly developed Sn/Cu plating process allows for a simultaneous plating of both sides of IC Substrates, the C4 and the BGA side of the panel. On the C4 side the complete Sn/Cu solder ball is plated whereas on the BGA side the basis for the subsequent placement of a larger solder ball can be achieved. Examples are given for such a process flow using the photo resist process on top of a solder resist. As a further development of the solder bumping process the photo resist free sequence is introduced which uses a modified tin deposition electrolyte to produce tin filled structures directly onto the structured and prepared soldermask. This process offers optimum solder bump plated distribution and the potential for further cost savings due to the elimination of critical processing steps associated with photo imaging.

Horizontal systems: Leading technology for next generation HDI production

The developments in high density interconnect, HDI technology are characterized by the following: - Ever higher packaging density. - Reduction in line and space. - New dielectrics to meet high frequency demands. - Employment of thinner substrates. - Environmental and legislative impact. - Requirement for high overall process yields. - Demand for continuous reduction in process costs.