Taiga Takata

Cell library development methodology for throughput enhancement of character projection equipment

We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.

Technology mapping technique for throughput enhancement of character projection equipment

The character projection is utilized for maskless lithography and is a potential for the future photomask manufacture. The drawback of the character projection is its low throughput and leads to a price rise of ICs. This paper discusses a technology mapping technique for enhancing the throughput of the character projection. The number of EB shots to draw an entire chip determines the fabrication time for the chip. Reduction of the number of EB shots, therefore, increases the throughput of character projection equipment and reduces the cost to produce ICs. Our technology mapping technique aims to reduce the number of EB shots to draw an entire chip for increasing the throughput of character projection equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with an conventional technology mapping, our technology mapping technique achieved 19.6% reduction of the number of EB shots without any performance degradation of ICs. Moreover, our technology mapping technique achieved 48.8% reduction of the number of EB shots under no performance constraints. Our technique is easy for both IC designers and equipment developers to adopt because it is a software approach with no additional modification on character projection equipment.

A character size optimization technique for throughput enhancement of character projection lithography

We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing

A CP mask development methodology for MCC systems

The character projection (CP) is utilized for maskless lithography and is a potential for the future photomask manufacture because the CP can project ICs faster than the point beam projection and the variable-shaped beam (VSB) projection. The drawback of the CP is its lower throughput than that of photomask-based lithography and the amortization cost of CP equipment leads to the price rise of ICs. This paper discusses a CP mask development methodology for increasing the throughput of MCC systems. The proposed methodology virtually increases the number of the logic cells which are projected with the CP. In the proposed methodology, the multiform CP masks are utilized among the column-cells for reducing the VSB projection. The experimental results show that the proposed CP mask development methodology reduced 71.3% of the number of EB shots needed for an SCC system. It also reduced 42.6% of the number of EB shots needed for the MCC system in which uniform CP masks are utilized for all column-cells.

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits

Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand, a heuristic algorithm AnSER can analyze logic masking effects approximately in runtime proportional to circuit size. AnSER, however, is possible to analyze logic masking effects optimistically especially for circuits protected with spatial redundancy, which might not be suitable for soft error tolerant designs. This paper shows a robust algorithm to analyze logic masking effects pessimistically. Pessimistic analysis is guaranteed with employing the proposed algorithm, while the computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than a fault-simulation-based exact algorithm with 11.5% overestimate for average susceptibility to errors. For circuits partially protected with spatial redundancy, the proposed algorithm has estimated average susceptibility with 37.9% overestimates on average, while AnSER has estimated average susceptibility with 96% underestimates on average.

Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs

In this paper we present the post-processing algorithm, cut substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUTs network whose area is minimum under depth minimum constraint seems to be as difficult as NP-hard class problem. Cut substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.

Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems

We propose a cell library development methodology for throughput enhancement of electron beam direct-write (EBDW) systems. First, an ILP (integer linear programming)-based cell selection is proposed for EBDW systems in which both of the character projection (CP) and the variable shaped beam (VSB) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed to increase the number of cells on a CP aperture mask. Finally, a case study is shown in which the numbers of EB shots are examined under several cases.

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits

This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30–143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7–17 times faster with only 0.5–2.2% estimation error.

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

Recent technology mappers for LUT-based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long run-time. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottom-up merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K=8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K=8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4% larger than that derived by exhaustive enumeration on average, and the depth is the same.

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)

Technology mapping for LUT-based FPGAs can be formulated as DAG covering problem that is to cover given Boolean network with a set of subgraphs called cones, which is known to be NP-hard. So far, no efficient algorithm exists to solve it exactly. Existing technology mappers employ cost flow which is a heuristic metric to indicate how good a cone is for total cost, i.e. area or power. The estimation of total cost based on cost flow might be inaccurate because it does not consider multiple fanouts adequately. This paper proposes a novel method to compute the lower bound for DAG covering problem by transforming a DAG into a tree graph. A novel mapping algorithm with weighted cost flow based on the lower bound is also presented. Weighted cost flow considers the effect of multiple fanouts accurately. Cone Resubstitution: an existing post-processing of technology mapping to reduce area/power by removing unnecessary node duplications is employed. The experimental results show that the proposed method generates networks whose average area is 7%, 7%, 10% smaller than that generated by DAOmap for K = 4, 5, 6 respectively. It is also shown that the proposed method works better than the combination of a mapper based on traditional cost flow and Cone Resubstitution. On the other hand, the proposed method generates LUT networks whose dynamic power is 10% smaller than that generated by Emap for K = 4 on average.