Takaharu Itani

Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.

Improvement of threshold voltage roll-off by ultra-shallow junction formed by flash lamp annealing

Flash lamp annealing (FLA) was first applied to complementary MOSFETs (CMOS) as a new method of activating implanted impurities in source and drain. By optimizing ion implantation and activation annealing conditions, junction depth less than 10 nm with good junction leakage were successfully obtained for both p/sup +//n and n/sup +//p junctions. Threshold voltage (V/sub th/) roll-off characteristics for MOSFETs fabricated by FLA show drastic improvement as compared with conventional spike annealing.

Optical interference effect on chip’s temperature distribution in the optical annealing process

In the optical annealing process, temperature distributions of chips on a silicon wafer tend to be inhomogeneous. One of sources to generate the temperature inhomogeneities should be an optical interference effect of the incident lights where the incident lights are interfered by chip’s circuit patterns which are small enough compared to the wavelength. The optical interference effect disturbs optical absorption distribution of a chip, which makes the temperature distributions inhomogeneous. To estimate the optical absorption distribution of a chip, the optical absorptions against various circuit patterns are calculated with RCWA (Rigorous Coupled Wave Analysis) simulations. With the estimated optical absorption distribution, the temperature distribution is calculated by a heat diffusion simulation. The simulated temperature distribution agreed well with experimental result. This fact showed that the optical interference effect should be the main source of the temperature inhomogeneities. Moreover, our method proved to be appropriate to predict the temperature distributions of chips with good accuracy.

Impact of Flash Lamp Annealing on 20-nm-Gate-Length Metal Oxide Silicon Field Effect Transistors

The advantages of using the new flash lamp annealing (FLA) technology and a shallow junction with the consequent low sheet resistivity for metal oxide silicon field effect transistors (MOSFETs) with gate length (L) of 20 nm were clarified by computer simulations based on MOSFETs fabricated with FLA for the first time. In contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |Ioff| with a low channel surface dopant concentration, thus providing a higher mobility value and a higher drive current. FLA is promising for improving the performance of sub-30-nm-gate-length MOSFETs.