Toshihiko Iinuma

10-15 nm ultrashallow junction formation by flash-lamp annealing

Flash-lamp annealing (FLA) technology, a new method of activating implanted impurities, is proposed. FLA is able to reduce the time of the heating cycle to within the millisecond range. With this technology, an abrupt profile is realized, with a dopant concentration that can exceed the maximum carrier concentration obtained by conventional rapid thermal annealing (RTA) or furnace annealing. In contrast to a laser annealing method, FLA can activate dopants in an 8-inch-diameter substrate and, simultaneously, strictly control diffusion of dopants so as not to melt the substrate surface by radiation. FLA presents the possibility of fabricating sub-0.1-µm MOSFETs with good characteristics.

Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.

Flash Lamp Anneal Technology for Effectively Activating Ion Implanted Si

Device miniaturization requires reduction of the thermal budget in the annealing process for ultra-shallow junction and ultra-thin gate oxide. Recently, spike anneal technology has considerably reduced the time of the heating cycle. In heating the substrate above 1000°C, however, the total time of ramp-up and rampdown takes 10 sec or above. In order to minimize the heating cycle, we newly developed a flash lamp anneal (FLA) technology. FLA was able to reduce the heating cycle within the millisecond range and was successfully applied to activation process by combining appropriate assist heating. In this paper, we first report fundamental results on electrical activation of impurities by using FLA technology.

Advanced Ion Implantation Technology for High Performance Transistors

Cryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs. In order to improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed. In this technology, chip-by-chip implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size.

Flash lamp annealing technology for ultra-shallow junction formation

As a new method of activating implanted impurities, flash lamp annealing (FLA) technology is proposed. By optimizing FLA and implantation conditions, junction depth of 14 nm and the sheet resistance of 770 /spl Omega//sq. with good junction leakage were successfully obtained for p/sup +//n junctions without wafer slip and warpage problems.

Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics

Damascene metal gate MOSFETs with Co silicided source/drain and high-k dielectrics were successfully formed without agglomeration of CoSi/sub 2/ films. Good transistor characteristics were reproducibly obtained and shorter inverter delay was confirmed by 151 stage CMOS ring oscillators.

Pt Segregation at the NiSi/Si Interface and a Relationship with the Microstructure of NiSi

Nickel monosilicide (NiSi) is used for lowering the parasitic resistances in source/drain. However, NiSi has a disadvantage of lower thermal instability such as NiSi2 nucleation and agglomeration. We first reported Pt segregation was found at a NiSi/Si interface by Atom Probe (AP) analysis.[6] In this study, we found that the scheme of Ni silicide grain growth and the resultant NiSi crystal shape is strongly affected by the existence of Pt by utilizing AP analysis, TEM and FE-SEM. AP observations were carried on a Ni-Pt as sputterd sample and on a Ni-Pt as annealed sample. The depth profile for the sample after silicidation indicates Pt atoms are segregated at a NiSi surface and NiSi/Si interface. For the analysis of the Pt distribution in the sample after silicidation in more details, we thoroughly analyzed the 3D image as follows: a cylindrical part is extracted from the 3D image; it is divided into 5nm thick slices; and 2D images depicting density-distribution of Pt and As. From these 2D images, we found Pt atoms exist around NiSi grains. The Atom Probe result indicates that Pt atoms segregate at the NiSi surface, grain boundaries and NiSi/Si interface. Plane view TEM and FE-SEM observations were carried out on Ni(Pt) silicide and on Ni silicide without Pt to find the influence of the segregated Pt atoms on the microstructure of NiSi. The spindle shape of NiSi(w/o Pt) grains were observed on the former. On the other hand, we observed on the latter that the Pt addition affected the shape of the NiSi grains and changed NiSi grains to round polygonal shape and the average grain size became smaller. It can be said that the Pt addition suppresses a crystal growth along in a longitudinal direction of a grain. We speculate that fine round shape NiSi grains are formed as a result of the suppression of the anisotropic crystal growth by Pt segregation, and provide the improvement of the thermal stability of the NiSi film.

Silicide technology for USJ in next technology node

Silicide technology for ultra-shallow junction in next technology node is discussed. Salicide material is changed from low resistivity refractory metal silicide to near-noble metal silicide from the view point of less consumption of Si by silicidation. The pn junction leakage for shallow S/D can be drastically improved by NiSi as compared with CoSi/sub 2/.

Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs

This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of ultra-rapid thermal annealing technology such as advanced spike RTA, laser annealing, SPE, flash lamp annealing are compared. Issues of this technology are simultaneously accomplishing ultrashallow Xj, lower sheet resistance and lower crystal damage density for fabricating advanced MOSFETs. By optimizing various process conditions, we can successfully obtain ultra shallow p+/n and n+/p junction of less than 10 nm. In this paper, we overview the prospects for ultra-rapid thermal process for advanced CMOSFETs.

Reduction in pn Junction Leakage for Ni-Silicided Small Si Islands by Using Improved Convection Annealing

In conventional self-aligned nickel (Ni) silicide (SALICIDE) process, Ni silicidation is usually carried out by using tungsten–halogen lamp annealing and pn junction leakage current increases with the miniaturization of junction area and depth. The junction leakage is closely related to Ni-silicide thickness determined by absorption coefficient of infrared light from the halogen lamp. We proposed a new method for Ni silicidation based on natural convective heat transfer to the wafer and confirmed that this method can drastically improve the pattern dependence of pn junction leakage because of better uniformity of Ni-silicide thickness independent of pattern size of active areas.