Kyoichi Suguro

Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFETs was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFETs also operated at higher speed. >

10-15 nm ultrashallow junction formation by flash-lamp annealing

Flash-lamp annealing (FLA) technology, a new method of activating implanted impurities, is proposed. FLA is able to reduce the time of the heating cycle to within the millisecond range. With this technology, an abrupt profile is realized, with a dopant concentration that can exceed the maximum carrier concentration obtained by conventional rapid thermal annealing (RTA) or furnace annealing. In contrast to a laser annealing method, FLA can activate dopants in an 8-inch-diameter substrate and, simultaneously, strictly control diffusion of dopants so as not to melt the substrate surface by radiation. FLA presents the possibility of fabricating sub-0.1-µm MOSFETs with good characteristics.

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

A NiSi salicide technology for advanced logic devices

A nickel-silicide (NiSi) technology for deep submicron devices has been developed. It was confirmed that Ni films sputtered on n- and p-single and polysilicon can be changed to mono-silicide (NiSi) stably at low temperature (600 degrees C) over a short period without any agglomeration. The NiSi layer did not absorb boron or arsenic atoms during silicidation, and a high concentration of boron or arsenic was achieved at the silicide/silicon interface, contributing to a low contact resistance. NiSi technology was applied to a dual-gate CMOS structure. Excellent pn junction characteristics and high drivabilities of both the n- and p-MOSFETs were successfully obtained.<<ETX>>

Improvement of threshold voltage deviation in damascene metal gate transistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Self‐aligned passivation on copper interconnection durability against oxidizing ambient annealing

A self‐aligned niobium (Nb) passivation method has been developed in order to improve the stability of copper (Cu) in an oxidizing ambient. A Cu/Nb/SiO2/(100)Si structure was annealed between 400 and 850 °C for 30 min in a gas mixture of H2 and N2. The underlying Nb diffused to the Cu surface and turned into its nitride at 750 °C. The surface Nb nitride layer acted as a passivation layer against oxidation. The passivated Cu was found to retain its resistivity of 2.0 μΩ cm even after oxidation at 400 °C for 30 min in a dry oxygen ambient.

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate