Kazumi Nishinohara

Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage

The effects of fluctuations in dopant distribution on the MOSFET threshold voltage and their dependence on the scaling were investigated using device simulation. The simulation indicates that the microscopic fluctuations in dopant distribution not only induce threshold-voltage value. It was found that the threshold-voltage value deviation is mostly affected by fluctuating dopant distribution at the substrate surface, rather than throughout the depletion layer. Discussion incorporating microscopic fluctuations in surface electric potential, due to fluctuating dopant distribution, explained not only deviations but also the mean value lowering of the threshold voltage in the simulation. >

Improvement of threshold voltage roll-off by ultra-shallow junction formed by flash lamp annealing

Flash lamp annealing (FLA) was first applied to complementary MOSFETs (CMOS) as a new method of activating implanted impurities in source and drain. By optimizing ion implantation and activation annealing conditions, junction depth less than 10 nm with good junction leakage were successfully obtained for both p/sup +//n and n/sup +//p junctions. Threshold voltage (V/sub th/) roll-off characteristics for MOSFETs fabricated by FLA show drastic improvement as compared with conventional spike annealing.

Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |I/sub off/| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs.

Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs

This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of ultra-rapid thermal annealing technology such as advanced spike RTA, laser annealing, SPE, flash lamp annealing are compared. Issues of this technology are simultaneously accomplishing ultrashallow Xj, lower sheet resistance and lower crystal damage density for fabricating advanced MOSFETs. By optimizing various process conditions, we can successfully obtain ultra shallow p+/n and n+/p junction of less than 10 nm. In this paper, we overview the prospects for ultra-rapid thermal process for advanced CMOSFETs.

Surface Channel Metal Gate Complementary MOS with Light Counter Doping and Single Work Function Gate Electrode

We propose a channel engineering guideline for the low threshold voltage (Vth) metal oxide silicon field effect transistor (MOSFET) with metal gate, which is promising for highly miniaturized MOSFETs. For lowering Vth of metal gate MOSFET, counter doping is useful. However, a buried channel with heavy counter doping has several disadvantages, such as the degradation of subthreshold swing. In this work, using a design with light counter doping, a surface channel complementary metal oxide silicon (CMOS) of low Vth with a single work function gate electrode was successfully fabricated showing superior characteristics. Device simulation was used to investigate the impacts of the channel profile of such a device. It was found that using counter doping with low concentration to an optimized depth results in better subthreshold characteristics than that using shallow counter doping with high concentration. A lower counter dopant concentration also suppresses Vth deviations. The damascene gate process was used in the fabrication.

Impact of Flash Lamp Annealing on 20-nm-Gate-Length Metal Oxide Silicon Field Effect Transistors

The advantages of using the new flash lamp annealing (FLA) technology and a shallow junction with the consequent low sheet resistivity for metal oxide silicon field effect transistors (MOSFETs) with gate length (L) of 20 nm were clarified by computer simulations based on MOSFETs fabricated with FLA for the first time. In contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |Ioff| with a low channel surface dopant concentration, thus providing a higher mobility value and a higher drive current. FLA is promising for improving the performance of sub-30-nm-gate-length MOSFETs.