Takaharu Tani

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C for 2 min and thinned down to 30-μm thickness. The DRAM cell characteristics, which show 50% failure at 200 μs, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 °C. Meanwhile, the DRAM cell array shows 50% failure at 70 μs after an intentional Cu diffusion from the backside surface for 30 min at 300 ° C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23 mm2 designed with 0.18 µm CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 Ω to 10 MΩ. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments.

Ultralow Power Operation of 3-D Stacked Retinal Prosthesis Chip with Edge Enhancement Function

To restore visual sensation of blind patients suffering from age-related macular degeneration (AMD) and retinitis pigmentosa (RP), retinal prostheses have been developed by several institutes. Since the retinal cells would be damaged by heating, the power consumption of the retinal prosthesis chip should be kept less than 19 mW/mm 2 . In this work, to reduce the power consumption of retinal prosthesis chip, effects of edge enhancement function implemented in retinal prosthesis chip were investigated in detail, and ultralow power operation of the chip was clearly demonstrated.