H. Naganuma

A very low area ADC for 3-D stacked CMOS image processing system

This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC array. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. To achieve extremely low circuit area and low power dissipation, ADC designed in the prototype chip for fundamental evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. An implemented 9-bit prototype in a 90 nm CMOS technology occupies 100×100 μm2, achieves an ENOB of 7.28 bit at a conversion rate of 4 MS/s. The power dissipation is 381μW with supply voltage of 1.0V and 4 MS/s conversion rate.

Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration

The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C for 2 min and thinned down to 30-μm thickness. The DRAM cell characteristics, which show 50% failure at 200 μs, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 °C. Meanwhile, the DRAM cell array shows 50% failure at 70 μs after an intentional Cu diffusion from the backside surface for 30 min at 300 ° C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

The Youngs modulus (E) of Si substrate begin to noticeably decrease below 50-μm thickness. The Youngs modulus in 30-μm thick Si substrate decreased by 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Youngs modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness is bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in the 20- μm thick chip is shortened by ~ 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell.

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure

In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 ×100 μm2.

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ~ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory

The Youngs modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Youngs modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Youngs modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness was bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreased chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in 20-μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects a minority carrier generation lifetime, consequently shortening the retention time of DRAM cell.

Fabrication and In vivo Evaluation of Poly(3,4-ethylenedioxythiophene) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

The development of poly(3,4-ethylenedioxythiophene) (PEDOT) stimulus electrodes and the relationship between the electrical stimulation of a rabbit retina and electrically evoked potential (EEP) were studied in detail. We fabricated implantable flexible cables with Pt, IrOx, and PEDOT electrodes and evaluated the electrochemical impedances (EIs) and charge injection capacities (CICs) of such electrodes. From the result, we confirmed that PEDOT electrodes have both lower EIs and larger CICs than Pt and IrOx electrodes. In addition, we performed in vivo experiments with PEDOT electrodes and clarified the relationships between the electrical stimulation of the rabbit retina and EEP. It is highly probable that visual restoration will be realized safely with PEDOT electrodes.

Ultralow Power Operation of 3-D Stacked Retinal Prosthesis Chip with Edge Enhancement Function

To restore visual sensation of blind patients suffering from age-related macular degeneration (AMD) and retinitis pigmentosa (RP), retinal prostheses have been developed by several institutes. Since the retinal cells would be damaged by heating, the power consumption of the retinal prosthesis chip should be kept less than 19 mW/mm 2 . In this work, to reduce the power consumption of retinal prosthesis chip, effects of edge enhancement function implemented in retinal prosthesis chip were investigated in detail, and ultralow power operation of the chip was clearly demonstrated.

Development and In Vivo Evaluation of Conductive Polymer (PEDOT) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

1 Department of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6258, Fax: +81-22-795-6908, E-mail: link@lbc.mech.tohoku.ac.jp 2 Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 3 Department of Chemistry and Bioengineering, Faculty of Engineering, Iwate University