Toshiaki Hanibuchi

Semiconductor logic integrated circuit device having first and second operation modes for testing

A semiconductor logic integrated circuit device comprising a signal selection means and a storing means, which is capable of adjusting the logic levels of an output signal therefrom. With such a circuit device, the signal selection means and the storing means are controlled in normal operation mode so that a parallel input signal is allowed to be output as a parallel output signal from output terminals of the circuit device after subjecting the parallel input signal to logical signal processing. On the other hand, the signal selection means and the storing means are controlled in a testing opertion mode so that the parallel input signal are output in serial mode from a serial signal output terminal of the circuit device, and a serial input signal to the signal selection means is allowed to be stored in the storing means to adjust the logic levels of the output signal from the circuit device at desired levels voluntarily.

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea-of-gates

To improve the density of BiCMOS sea-of-gates, bipolar and PMOS transistors are merged to form compact basic cells combined with the gate isolation technique. This structure occupies only 12% of the conventional bipolar transistor area. The density of the basic cell increases by 60% compared with conventional cells. The pull-up BiCMOS circuit achieves the fastest gate delay of 200 ps. A 16-bit multiplier in the test chip fabricated with 0.8 mu m BiCMOS technology operates at 18 ns delay time.<<ETX>>

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates

A compact basic cell for BiCMOS sea-of-gates (SOG) circuits was developed using a bipolar-PMOS merged structure and gate-isolated bipolar transistors. The new cell structure reduces the cell area using the bipolar-PMOS merged transistors. The cell has no restrictions regarding macrocell placement because it has no shared element. The cell density is 60% higher than that of conventional cells. Three types of circuits are provided for a macrocell using the basic cell. The pull-up BiCMOS circuit, one of the circuit alternatives, obtains the shortest gate delay with average load capacitance and high density comparable to a pure CMOS density. The gate delay of 200 ps was achieved with the pull-up BiCMOS two-input NAND gate fabricated with 0.8- mu m BiCMOS technology. >

0.5 micron low-power BiCMOS gate array for B-ISDN 622 Mb/s user-network interface

A 0.5 micron low power BiCMOS gate array for B-ISDN 622 Mb/s User-Network Interface (UNI) is described. The gate array provides both 3k-gate ECL master array and 500 K-gate CMOS master array. It also offers ECL/TTL/CMOS mixed-level interface with dual power supply scheme (+3.3 V/-2 V) with low power consumption. The new ECL I/O buffers suitable to this scheme consume the power of 10 mW and 20 mW, respectively. A MUX/DEMUX on the ECL master array has been achieved with the power consumption 130 mW using LCML series-gates operating at the power supply of +3.3 V. The gate array is capable of realizing 4 pairs of 622 Mb/s UNI on a single chip with the power consumption of 4.3 W.<<ETX>>