Sadami Takeoka

On validating data hold times for flip-flops in sequential circuits

We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits.

Design for testability using register-transfer level partial scan selection

An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.

On effective criterion of path selection for delay testing

Since a logic circuit often has too many paths to test delay of all paths in the circuit, it is necessary for path delay testing to limit the number of paths to be tested. Paths to be tested should be ones with large delay that more likely cause a fault. In addition, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate criteria of path selection for path delay testing. We first define typical two criteria to be investigated here, and then experimentally show the feature of paths selected with each criterion, with respect to fault coverage of other delay fault models. From our experiments, we observe that test patterns for the longest paths cannot cover many other faults such as gate delay faults or segment delay faults.

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis

We propose a method to estimate fault efficiency of test patterns for path delay faults. In path delay fault testing, fault coverage of test patterns is usually very low, because circuits have not only a lot of paths but also a lot of untestable paths. Although fault efficiency would be better metric to evaluate test patterns rather than fault coverage, it is too difficult to compute it exactly, if we do not compute the total number of untestable paths exactly. The proposed method samples a part of paths after untestable path analysis, and estimate fault efficiency based on the percentage of untestable paths in the sample paths. Through our experimental results, we show that the proposed method can accurately estimate fault efficiency of test patterns in a reasonable time. Also, since the accuracy of fault efficiency estimated with the proposed method depends on how to sample the paths, we look into the influence of path sampling methods to the accuracy in the experiments.