Takahiro Shima

A 60 GHz fully integrated CMOS transceiver with amplitude/phase imbalance cancellation technique

A 60 GHz direct conversion transceiver which employs amplitude/phase imbalance cancellation technique is newly proposed. By using the proposed technique, the receive path of the transceiver achieves less than 0.2 dB of amplitude error and less than 3° of phase error at 60 GHz bands over 10 GHz bandwidth, which relaxes the design accuracy required for baluns used in the transceiver. The transceiver, which fully integrates a phase locked loop (PLL) and analog low pass filters, is implemented in 90 nm CMOS technology, achieving a low power consumption of 230 mW in transmit mode and 173 mW in receive mode. The output spectrum of 1.76 Gbps π/2-BPSK modulation shows the excellent distortion and spurious suppression that meet the IEEE802.11ad draft standard.

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A 60 GHz phase-locked loop (PLL) synthesizer with an injection locked frequency divider (ILFD) is presented. The PLL employs a simple and fast calibration algorithm consisting of the VCO sub-band selection and the adjustment of the ILFD locking range. The proposed PLL is demonstrated using 90 nm CMOS. The calibration process converges within 100 μsec at all 4-channels defined by the Wireless Gigabit Alliance (WiGig).