Takamasa Usui

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi xOy barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSixOy layer was formed at the interface of Cu and dielectric SiO2, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO2, suggesting that MnSixOy layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via

Effect of Plasma Treatment and Dielectric Diffusion Barrier on Electromigration Performance of Copper Damascene Interconnects

The effect of plasma treatment and a dielectric diffusion barrier on electromigration (EM) performance was examined. The characteristics and adhesion properties at the interface between copper (Cu) and the dielectric diffusion barrier were also investigated by scanning transmission electron microscopy–electron energy loss spectrometry (STEM–EELS). The existence of oxygen at the interface after hydrogen (H2) plasma treatment, which has a large pre-exponential factor, causes a large EM drift velocity. Ammonium (NH3) plasma treatment can reduce the Cu oxide completely, resulting in an improvement in EM performance. On the other hand, the dielectric diffusion barrier of SiCxNy, which has a better adhesion property then SiCx, reduces EM drift velocity and provides a larger activation energy. The reduction of CuOx completely by plasma treatment is essential and the selection of dielectric diffusion barrier is important to improve the EM performance of Cu damascene interconnects.

Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM

100 nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65 nm-node Cu metallization with excellent reliability.

Electromigration diffusion mechanism of electroplated copper and cold/hot two-step sputter-deposited aluminum-0.5-wt% copper damascene interconnects

The electromigration (EM) diffusion mechanisms of electroplated copper (Cu) with tantalum (Ta) barrier/dielectric diffusion barrier SiCxNy and cold/hot two-step sputter-deposited aluminum (Al)–0.5-wt%Cu damascene interconnects with niobium (Nb) liner are examined and compared using the via-EM testing pattern with different linewidths. The interface between Cu and SiCxNy is the dominant diffusion path for the Cu damascene interconnects regardless of the Cu microstructure. An activation energy (Ea) of approximately 0.9±0.03eV is obtained for the width range of 0.1–6μm. Therefore, the diffusion mechanism is independent of the Cu microstructure. Regarding the cold/hot two-step sputter-deposited Al–0.5-wt%Cu damascene interconnects with Nb liner, the EM median time to failure (MTF) increases with increasing the linewidth for the Al bamboolike microstructure, indicating that the interface between the Al and Nb liners is the dominant diffusion path. This is probably because a rapid diffusion path along the NbAlx...

EM lifetime improvement of Cu damascene interconnects by p-SiC cap layer

Mean time to failure (MTF) of Cu damascene interconnects with p-SiC cap layer is achieved to be approximately 2 times as long as that with conventional p-SiN cap layer. This improvement can be explained by the difference of adhesion between Cu and the cap layer. It is also found that Cu dominant diffusion path is the interface between Cu and the cap layer for Cu interconnects with TaN/Ta and p-SiC, p-SiN.

High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node

In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3.5) and dual hard mask process using a metal layer was proposed to reduce the capacitance of dielectric diffusion barrier and protection layers in hybrid (PAr/SiOC) inter-layer dielectric (ILD) structure. As for the metallization, a self-formed MnSixOy barrier technology was applied in hybrid ILD structure. Drastic reduction of via resistance and excellent electromigration and SiV performance were obtained for the first time in hybrid ILD structure

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

Identification of electromigration dominant diffusion path for Cu damascene interconnects and effect of plasma treatment and barrier dielectrics on electromigration performance

Electromigration testing pattern to identify the dominant diffusion path of Copper (Cu) damascene interconnects is proposed. It is confirmed that dominant diffusion path is the interface between Cu and barrier dielectrics using the proposed testing pattern. After identification of the dominant path, the effects of the plasma treatment and barrier dielectric SiC/sub x/N/sub y/ and SiC/sub x/ on the EM performance is investigated. Failure analysis reveals that Cu oxide at the interface of SiC/sub x/ samples with H/sub 2/ plasma treatment accelerates the Cu EM diffusion, resulting in lower activation energy and shorter lifetime. In addition, it is also found that nitrogen at the interface retards Cu diffusion drastically.

Electromigration of Al-0.5 wt%Cu with Nb-Based Liner Dual Damascene Interconnects

The electromigration (EM) of Al-0.5 wt%Cu/Nb-based liner dual damascene (DD) interconnects is investigated for the first time. It is found that EM-induced voids nucleate in the line around the via at the cathode end of the line and their number decreases as the distance from the via becomes longer for the tungusten (W)-single damascene (SD)/aluminum (Al)-dual damascene (DD) interconnects. This fact indicates W-SD/Al-DD interconnects has mono-modal EM failure. Regarding the Al-SD/Al-DD interconnects, two types of layered liner, niobium (Nb)/long throw sputtered (LTS)-niobium nitride (NbN)/Nb and Nb/self ionized sputtered (SIS)-NbN/Nb, are applied and the EM failure mode is investigated. It is found that the Nb/LTS-NbN/Nb liner sample has bi-modal failure, which manifests as normal failure similar to W-SD/Al-DD interconnects and failure with long time to failure (TTF), probably due to the continuous atom flow at the sidewall or bottom of the via in the lower Al-SD interconnects. On the contrary, the Nb/SIS-NbN/Nb liner sample has mono-modal failure with a tight distribution of the EM log-normal distribution, resulting in a high EM reliability.