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Featured researches published by Sachiyo Ito.


Japanese Journal of Applied Physics | 2004

Electromigration of Al-0.5 wt%Cu with Nb-Based Liner Dual Damascene Interconnects

Takamasa Usui; Tadayoshi Watanabe; Masaaki Hatano; Sachiyo Ito; Junichi Wada; Hisashi Kaneko

The electromigration (EM) of Al-0.5 wt%Cu/Nb-based liner dual damascene (DD) interconnects is investigated for the first time. It is found that EM-induced voids nucleate in the line around the via at the cathode end of the line and their number decreases as the distance from the via becomes longer for the tungusten (W)-single damascene (SD)/aluminum (Al)-dual damascene (DD) interconnects. This fact indicates W-SD/Al-DD interconnects has mono-modal EM failure. Regarding the Al-SD/Al-DD interconnects, two types of layered liner, niobium (Nb)/long throw sputtered (LTS)-niobium nitride (NbN)/Nb and Nb/self ionized sputtered (SIS)-NbN/Nb, are applied and the EM failure mode is investigated. It is found that the Nb/LTS-NbN/Nb liner sample has bi-modal failure, which manifests as normal failure similar to W-SD/Al-DD interconnects and failure with long time to failure (TTF), probably due to the continuous atom flow at the sidewall or bottom of the via in the lower Al-SD interconnects. On the contrary, the Nb/SIS-NbN/Nb liner sample has mono-modal failure with a tight distribution of the EM log-normal distribution, resulting in a high EM reliability.


international reliability physics symposium | 1999

Significant improvement in electromigration of reflow-sputtered Al-0.5wt%Cu/Nb-liner dual damascene interconnects with low-k organic SOG dielectric

Takamasa Usui; Toshiharu Watanabe; Sachiyo Ito; Masahiko Hasunuma; M. Kawai; Hisashi Kaneko

Reflow-sputtered Al-0.5wt%Cu/Nb-liner dual damascene interconnects with low-k organic spin-on glass (SOG) passivation were fabricated for the first time. A significant improvement in median time-to-failure (MTF) for electromigration (EM) was observed when the SOG was compared to a standard TEOS passivation. This improvement is due to the low Youngs modulus of the SOG, which suppresses stress evolution in the Al interconnects near the via during EM testing.


MRS Proceedings | 1995

A Highly Reliable Al Line with Controlled Texture and Grain Boundaries

Masahiko Hasunuma; H. Toyoda; T. Kawanoue; Sachiyo Ito; Hisashi Kaneko; M. Miyauchi

In order to clarify the relationship between Al line reliability and film microstructure, especially grain boundary structure and crystal texture, we have tested three kinds of highly textured Al lines, namely, single-crystal Al line, quasi-single-crystal Al line and hypertextured Al line, and two kinds of conventional Al lines deposited on TiN/Ti and on SiO2. Consequently, the empirical relation between the electromigration (EM) lifetime of Al line † and the (111) full width at half maximum (FWHM) value ω is described by † ∝ ω -2 [1]. This improvement of Al line reliability results from as following reasons; firstly, homogeneous microstructure and high activation energy of 1.28eV for the single-crystal Al line (ω=0.18°); secondly, sub-grain boundaries which consisted of dislocation arrays found in the quasi-single-crystal Al line (ω=0.26°) has turned out to be no more effective mass transport paths because dislocation lines are perpendicular to the direction of electron wind. Although there exist plural grain boundary diffusion paths in the newly developed hypertextured Al line (ω=0.5°) formed by using an amorphous Ta-Al underlayer {1], the vacancy flux along the line has been suppressed to the same order of magnitude of single crystal line. It has been clarified that the decrease of FWHM value has promoted the formation of sub-grain boundaries and low-angle boundaries with detailed orientation analysis of individual grains in the hypertextured film. The longer EM lifetime for the hypertextured Al line is considered to be due to the small grain boundary diffusivities for these stable grain boundaries, and this diffusivity reduction resulted in the suppression of void/hillock pair in the Al lines. These results have confirmed that controlling texture and/or grain boundary itself is a promising approach to develop reliable Al lines which withstand higher current densities required in future ULSIs.


Third international stress workshop on stress-induced phenomena in metallization | 2008

Effects of aluminum texture on electromigration lifetime

Hiroshi Toyoda; Takashi Kawanoue; Sachiyo Ito; Masahiko Hasunuma; Hisashi Kaneko

A hyper-textured aluminum (Al) film has been fabricated by using a newly developed amorphous tantalum-aluminum (Ta-Al) underlayer. The full width at half maximum (FWHM) value of the (111) rocking curve of the Al film has been attained to be 0.5 degrees. It has been shown that the electromigration (EM) lifetime of Al interconnections increased inversely proportional to the square of the FWHM value. This lifetime improvement has been attributed to the reduction of the vacancy flux along the grain boundaries. The analysis of the grain boundary structure in the hyper-textured Al film with the transmission electron microscope (TEM) has revealed that the texture improvement not only eliminates the twist component of the boundary mismatch, but also controls the tilt one. It has been also clarified that the compressive stress relaxation and the hillock formation of Al film during the thermal cycling were restrained by the hyper-texture. This phenomenon has been well explained by the grain boundary diffusion suppr...


STRESS‐INDUCED PHENOMENA IN METALLIZATION: Ninth International Workshop on Stress‐Induced Phenomena in Metallization | 2007

Nanometer‐Scale Stress Field Evaluation of Cu/ILD Structure by Cathodoluminescence Spectroscopy

Masako Kodera; Sachiyo Ito; Masahiko Hasunuma; Shigeru Kakinuma

Engineering of the residual stress fields related to the backend process of LSI devices with Cu interconnects is required together with the adoption of low‐k materials that have quite low Youngs modulus. We measured the nano‐scale residual stresses stored within interlayer dielectric (ILD) films according to a cathodoluminescence (CL) piezo‐spectroscopic technique. The SiO2 film (k = 4.1) produced a sharp and stable spectrum, which well suited for the analysis of stress distribution on the surface. We confirmed that stresses in ILD could be successfully detected with less than 50 nm spatial resolution and that a higher chemical mechanical polishing (CMP) downward pressure led to a shift toward the tensile side of the residual stress field stored in the ILD film. We also carried out line‐scan analyses of a cross section as well as a surface of the sample. Furthermore, we performed thermal stress analyses by FEM and made a comparison with the CL results. The tensile stress peak neighboring a Cu line observ...


STRESS-INDUCED PHENOMENA IN METALLIZATION: Seventh International Workshop on Stress-Induced Phenomena in Metallization | 2004

Interfacial Adhesion Study for Multi‐Layer Structures with m‐ELT Method and FEM Simulation

Masahiko Hasunuma; Sachiyo Ito; Hideyoshi Kittaka

The m‐ELT method is widely used because of the simplicity. And the fracture mode of this method is similar to that of the actual TCT (Temperature Cycling Test) that is used for the reliability test of an LSI package. In this method, only the thermal stress that is stored in epoxy has been taken into consideration and the effects of very thin ILD layers have been ignored. In this study, we have considered a crack initiation state, so we have paid our attention to the thermal stress singularity field generated in the free edge of ILD in m‐ELT measurement. We have evaluated the fracture toughness with two stress singularity parameters, lambda and Kf, in the tensile singular stress produced in ILDs’ interface near the slit tip. And we have elucidated the effect of low‐k film thickness and the effect of multiple‐layer stacking modules that have plural identical interfaces by the m‐ELT and FEM (finite element method) for the stress simulation. Especially the free‐edge interface between SiOC and SiCN has been di...


Archive | 1995

Method for production of semiconductor device

Masahiko Hasunuma; Sachiyo Ito; Keizo Shimamura; Hisashi Kaneko; Nobuo Hayasaka; Junsei Tsutsumi; Akihiro Kajita; Junichi Wada; Haruo Okano


Archive | 2003

Wiring structure of semiconductor device

Noriaki Matsunaga; Takamasa Usui; Sachiyo Ito


Archive | 1996

Electronic parts and manufacturing method thereof

Hiroshi Toyoda; Hisashi Kaneko; Masahiko Hasunuma; Takashi Kawanoue; Hiroshi Tomita; Akihiro Kajita; Masami Miyauchi; Takashi Kawakubo; Sachiyo Ito


Archive | 2009

SOLID-STATE IMAGE PICKUP APPARATUS AND CAMERA MODULE

Mie Matsuo; Sachiyo Ito

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