Takamitsu Kawahara

3C-SiC hetero-epitaxial growth on undulant Si(0 0 1) substrate

Abstract A novel technique to eliminate planar defects in the 3C-SiC hetero-epitaxial layer on Si substrate was developed. Before growing 3C-SiC, countered slopes oriented in the [1 1 0] and [ 1 1 0] directions were formed over the entire surface of Si (0 0 1) substrate (undulant-Si). In the initial stage of 3C-SiC growth, step flow epitaxy occurred on the surface slopes of the substrate, reducing the anti-phase boundaries. Continuous, twin boundaries (TBs) were arranged in parallel along the (1 1 1) or ( 1 1 1) planes. The twin boundaries were eliminated through combination of the countered TBs with 3C-SiC growth. Finally, no planar defects were observed on the surface of 200-μm thick 3C-SiC grown on “Undulant-Si”.

‘Switch-Back Epitaxy’ as a Novel Technique for Reducing Stacking Faults in 3C-SiC

A new technique that reduces stacking fault (SF) density in 3C-SiC, termed switch-back epitaxy (SBE), is demonstrated regarding its effects on morphological and electrical properties. SBE is a homoepitaxial growth process on backside of 3C-SiC grown on undulant-Si. The key feature of SBE, the surface polarity of residual SFs in 3C-SiC, which cannot be erased by heteroepitaxial growth on undulant-Si, is converted from the Si-face to the C-face. The SF density on the surface of 3C-SiC grown by SBE shows a remarkable decrease to one-seventh lower than that on undulant- Si. The leakage current of pn-diode epitaxially fabricated on the 3C-SiC substrate grown by SBE decreases to as low as one-thirtieth that on 3C-SiC substrate grown without SBE. These results suggest that SBE eliminates the SFs on the surface of 3C-SiC and subsequently reduces the leakage current at pn-junction thus fabricated.

Properties of Free-Standing 3C-SiC Monocrystals Grown on Undulant-Si(001) Substrate

Abstract. 3C-SiC was grown epitaxially on an “undulant-Si” substrate with countered slopes oriented in the [110] and [ -,1-,10] directions. Twinning domains in the ( -,111) or (1-,11) planes were annihilated by combining with counter-twinning domains, while those paral lel to (111) or ( -,1-,11) self-vanished. The free-standing 3C-SiC exhibited remarkable anisot ropy in its bending and electrical properties. The origin of these properties is dis cus ed by considering the lattice structure around the twinning domain.

Determination of densities and energy levels of donors in free-standing undoped 3C–SiC epilayers with thicknesses of 80μm

The densities and energy levels of donors in free-standing undoped 3C–SiC epilayers with the thicknesses of ∼80μm are investigated from the temperature dependence of the electron concentration n(T) obtained by Hall-effect measurements. Although in the analysis of n(T) many researchers usually assume that only one type of donor species is included in n-type 3C–SiC, no one knows whether this assumption is correct or not. In order to determine the densities and energy levels using n(T) without any assumptions regarding donor species, the graphical peak analysis method called free carrier concentration spectroscopy is applied. Three types of donor species are detected in these epilayers. These donor densities can be reduced to <5×1015cm−3 by growing 3C–SiC epilayers on undulant Si substrate. Moreover, the dependence of each donor level on a total donor density is investigated, which is used in 3C–SiC device simulation.

Propagation of Stacking Faults in 3C-SiC

To quantitatively evaluate the efficacy of stacking fault (SF) reduction methods, Monte Carlo simulations are carried out to reveal the SF distribution on a 3C–SiC (001) surface. SF density decreases with increasing epitaxial layer thickness and reducing size of the substrates. Additionally, SF density depends on interactions between adjoining SFs: annihilation of counter SF-pairs or termination of orthogonal SF-pairs. However, the SF is not entirely eliminated when growth occurs on undulant-Si or switchback epitaxy due to “spontaneous SF collimation”. The simulation shows that effective SF reduction methods, those that enhance the SF termination or annihilation, can theoretically attain the SF density on 3C–SiC (001) below 100 cm-1.

High Quality 3C-SiC Substrate for MOSFET Fabrication

Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm-1.

Correlation between Leakage Current and Stacking Fault Density of p-n Diodes Fabricated on 3C-SiC

The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.

Stacking Faults in 3C-SiC Relax Lattice Deformation

The microscopic structure around stacking faults (SF) in 3C-SiC w as observed using cross-sectional transmission electron microscopy. Domains separa ted by SF were displaced along the <111> direction from each other. The amount of displacement betwee n he domains depended on how many layers of Si-C pairs were involved in the SF. Therefore , SFs in 3C-SiC reduce the elastic lattice deformation by rearranging the structure and density with incr easing 3C-SiC thickness.

An Ultralow Stress Ta4B Absorber for X-Ray Masks

The stress controllability, stress uniformity, stress stability and dry etching characteristics of Ta4B films deposited by an in-line type sputtering system were investigated in detail. Low average stress Ta4B films within ±10 MPa have been fabricated on polished SiC films that demonstrate excellent reproducibility by step annealing. Stress uniformity of the film showed an approximate range of 7 MPa on a Si wafer in a 30 mm square area when the deposition conditions were modified. The Ta4B film demonstrated long-term stress stability and excellent resistance to the acid and water used in the cleaning process. The Ta4B film also ensures fine pattern formations below 0.2 µ m.

Reliable Method for Eliminating Stacking Fault on 3C-SiC(001)

A reliable method for reducing the stacking faults (SFs) is demonstrated on the 3C-SiC (001) surface. It is a practical method based on Monte Carlo (MC) simulations of SF propagation during 3C-SiC epitaxial growth, which showed that introducing some discontinuity on the (001) surface enhanced SF reduction. The method is implemented by patterning on the 3C-SiC (001) surface and subsequent homo-epitaxial growth, and this sufficiently reduced the SF density to less than 400 cm-1. A yield of 97.4 % was estimated for a device-ready area of 10 mm2 by statistical measurements of SF density on the entire epitaxial layer surface.