Tomohito Terasawa

An all-digital ADC/TDC for sensor interface with TAD architecture in 0.18-µm digital CMOS

An analog-to-digital and time-to-digital converter using a common architecture (Time A/D converter TAD) is presented. Its resolutions for both analog-to-digital converter (ADC) mode and time-to-digital converter (TDC) mode are settable. The circuit structure is a completely digital circuit including a ring-shaped pulse-delay-line (RDL) driven by an input voltage Vin, along with an RDL synchronous counter, latch, and encoder. A prototype TAD-IC core of 0.044 mm2 in a 0.18-µm digital CMOS achieved 3.1 mV/LSB (8-bit, 20-MS/s, 1.7 mW), 15 µV/LSB (16-bit, 100-kS/s, 1.3 mW) in ADC mode, and 126 ps/LSB (Vin = 1.8 V, 25-bit), 368 ps/LSB (Vin = 1.0 V, 25-bit) in TDC mode, respectively. As an actual example of high-resolution ADC, a radio-controlled clock (RCC) receiver IC prototype is implemented with a minimum detectable sensitivity of 0.7 µVrms.

All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches

Time analog-to-digital converters (TADs) based on the power-supply voltage dependence of CMOS gate propagation delay time can be constructed solely of CMOS digital circuits and are characterized by output of the time integral of input voltage, with no dead time. This paper describes digital quadrature detection (DQD) by TAD (TAD-DQD). With TAD-DQD, the in-phase and quadrature components of the input signal, including amplitude and phase information, can be obtained simply by adding and subtracting AD-converted TAD output using a sampling frequency that is four times the carrier frequency of the target signal. As an example of the application of TAD-DQD, the standard-time and frequency-signal receiver circuits of a radio-controlled clock/watch are shown, and the experimental results demonstrate that the time code can in fact be received.

An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS

TAD (Time A/D converter)-composite architecture with 4-shift-clock construction for both fast conversion and increased resolution is presented. An all-digital A/D converter using TAD architecture includes the following: 1) a ring-delay-line (RDL), that is a loop inverter chain, with 16 delay units (DUs), in which delay times are modulated by an A/D conversion voltage Vin for the DU supply voltage; 2) pulse latches; 3) an encoder; and 4) an RDL-frequency counter. The operating principle is to count the number of DUs through which the pulse passes within a sampling time interval Ts with (1/4)LSB-offset for 4-TAD-module by applying a new method named “Clock-Edge-Shift construction (CKES)” to achieve ADC speed-up and resolution-improvement effectively. The 15-bit TAD ADC with 1.2 mm2 using a 0.65-μm CMOS achieved both 2.9 mV/LSB at 10 MS/s and 5.7 mV/LSB at 20 MS/s, respectively, by applying the CKES construction with 4-TAD-composite core, resulting in the same level as 0.25-μm digital CMOS performance.

An all-digital PLL using frequency multiplying/dividing number with decimals in 0.18-μm digital CMOS

An all-digital PLL that generates arbitrary output clock frequencies with only one reference clock frequency is presented. The method adopted in this study uses multiplying/dividing numbers with decimals. A ring-delay-line (RDL) consisting of 32 stages makes it possible for both the frequency detector and digitally-controlled oscillator to have a common time base, resulting in this unique clock generator. Evaluation experiments were conducted using a 0.18-mum CMOS test chip of 0.096 mm2. In the case of a reference clock frequency of 60 kHz and multiplying number of 16.666, we confirmed a 999.96 kHz output clock with 11.6 ppm frequency error and 540 ps jitter standard deviation.

A 0.0027-mm 2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS

An all-digital A/D converter TAD (Time A/D converter) with 0.0027 mm2 is presented. The circuit structure is completely digital including a pulse-delay-line driven by Vin (input voltage), along with a counter, latch, and encoder. The TAD is easily shrinkable with the advancement in CMOS process technologies without any change of circuit architecture. Thanks to this construction, A/D conversion resolution with TAD method can automatically be improved. Their voltage resolutions of design rules from 0.8 µm to 65 nm are experimentally confirmed and compared, resulting in 80 times higher resolution of 65-nm TAD than that of 0.8-µm TAD. At the same time, the TAD core size is reduced less than 1/100. The unique TAD feature is that its resolution is settable by selecting sampling rates and power consumption is very low. For example, a prototype IC with 65-nm digital CMOS with 1.2-V supply voltage achieved 18.4-bit at 100-kS/s (1.11 mW), 10.8-bit 20-MS/s (1.13 mW), and 9.5-bit 50-MS/s (1.18 mW), respectively.

Electrostatically levitated ring-shaped rotational-gyro/accelerometer using all-digital OFDM detection with TAD

This paper presents a five-axis ring-MEMS rotational-gyro/accelerometer with an all-digital sensor circuit except for a C/V converter. For achieving all-digital construction, we apply Orthogonal Frequency Division Multiplexing (OFDM) using the all-digital TAD-OFDM concept for detecting multi-axis position signals of a single MEMS-ring element (dia. 1.5 mm), which is electrostatically levitated with a PWM-drive force-balance servo-system, using no analog elements after the C/V converter. In this sensor, seven carrier waves are set with specified frequencies arranged in accordance with power-of-two relationship including their π/2-phase-shift waves. Hence, the multiplex-detecting signals can be simultaneously demodulated just by using adders/subtractors. Thanks to this method, we can perfectly separate PWM-drive periods from multi-axis position sensing periods. In this study, the maximally-digital rotational-gyro/accelerometer performance with a 9-bit 25-MS/s TAD in a 0.65-μm CMOS and PWM-drive force-balance technology is experimentally confirmed with FPGA and DSP on the test board, achieving resolutions both 0.1 deg/s/LSB and 1 mG/LSB with a noise level of 0.03 deg/s/Hz1/2 and 0.3 mG/Hz1/2, respectively, without the need for any conventional ADCs and DACs.

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

An all-digital TAD-OFDM detection method for sensor interface with digital synchronous detection based on TAD (Time A/D converter)-type ADC is introduced. A TAD basic structure is a completely digital circuit including a ring-delay-line (RDL) with delay units (DUs) driven by an input voltage Vin and an RDL frequency counter, latch and encoder. Since the operating principle is to count the number of DUs through which the delay pulse passes within a sampling period Ts, this ADC (TAD) naturally performs as a Vin voltage-integration circuit for Ts. Hence, high frequency noises can be removed simultaneously with A/D conversion. First, as an example of a voltage-integration effect as a low-pass filter, magnet pick-up sensing was verified using a 22-bit TAD test chip fabricated using a 0.65-µm CMOS with 106 µV/LSB (100 kS/s). Next, the idea of digital synchronous detection with TAD (called TAD-DSD with the voltage-integration effect) is proposed. Finally, by using the TAD-DSD principle, TA-DOFDM detection is presented and experimentally confirmed, resulting in signal-detection of each wave-amplitude from a four-carrier-composite wave, which consists of frequencies, 1.6-, 3.2-, 6.4- and 12.8-MHz, respectively.

All-digital A/D converter TAD for high-resolution and low-power sensor/RF interface

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using entirely full-digital circuits, which deal with only two voltage levels (i.e., Vin-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation. The circuit architecture is completely digital, using a ring-delay-line RDL driven by an input voltage Vin as its power supply. Resolutions can be controlled by setting its conversion time Tcv, resulting in 16bit (1kS/s, 34μW) and 6bit (1MS/s, 48μW) with a prototype IC in a low-cost 0.65μm digital CMOS. As a scaling result based on the all-digital structure, higher performance of 0.18μm-test-IC with 28μV/LSB (160-kS/s) has been confirmed. Finally, as an RF digitization application, performance of time-domain processing as a mixer and ADC has been demonstrated achieving an FOM of ~35fJ/conversion-step with high resolution and low power for a 0.18μm one-chip radio-controlled clock (RCC) receiver IC.

All-Digital A/D converter TAD for sensor interface over wide temperature ranges

For achieving a highly-durable sensor ASIC with high performance and low cost, an all-digital sensor ADC using a time-domain processor TAD (Time A/D converter) is presented. Generally, measuring travel time of signals (e.g., light pulses, radio and ultrasonic waves, etc.) should be done under various stringent conditions (i.e., high ambient temperature) in automobiles, heavy-machinery and resource exploration systems, for example. Therefore, to realize wide-range temperature durability, sensor ADC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage Vin for its power supply, along with an RDL frequency counter, latch and encoder. In this study, an ADC core is implemented with 0.26 mm2 in a low-cost 0.35-μm digital CMOS applying our original 2-CKES (clock edge shift) method for higher resolution. When detecting low-level noisy signals received, a high-speed sensor ADC with a voltage resolution of 10.9 mV/LSB (6.5bit, 40MS/s) is available for integrating received pulse/wave amplitude to determine signal-travel time in a wide temperature range between -40 and 125°C. In addition, the all-digital architecture TAD is suitable for porting and scaling to another silicon technology with minimal IC design term and cost. As a scaling result, using a test-IC in a 0.18-μm digital CMOS, we have also experimentally confirmed its stable operations between -40 and 125°C with a smaller active area (0.044mm2) and higher resolutions, resulting in 0.15mV/LSB (1MS/s).

All-digital-ADC TAD in sensor digitization for scaling over wide temperature ranges

To achieve a highly-durable sensor ASIC/SoC with distinctive scalability for IoT (Internet-of-Things)-applications, an all-digital sensor ADC using TAD (Time A/D converter) in bulk CMOS is presented. Generally, sensors in automotive subsystems have to work under various stringent conditions (i.e., high ambient temperature). Therefore, to realize wide-range temperature durability, sensor ADC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage Vin for its power supply, along with an RDL frequency counter, latch and encoder. In the present study, first, an ADC core is implemented with 0.26 mm2 in a low-cost 0.35-μm digital CMOS with a voltage resolution of 10.9 mV/LSB (6.5bit, 40MS/s) in a wide temperature range between -40 and 125°C. Next, using a lower-cost 1.5-μm digital CMOS, a digital-type rotation-rate sensor with TAD has been developed over a wide temperature range between -40 and 150°C. Furthermore, other practical automotive sensors with TAD are introduced. Finally, thanks to the all-digital architecture, TAD is definitely suitable for scaling and porting to another silicon technology with minimal IC design term and cost. As scaling/porting results, using prototype ICs in 0.18/0.65-μm digital CMOS, we have experimentally confirmed their stable operation between -40 and 125°C with smaller/larger areas (0.044/0.29mm2) and higher/lower resolutions [(0.15mV/LSB)/(1.0mV/LSB) at 1MS/s,] respectively.