Takashi Hisada

Problems with wirebonding on probe marks and possible solutions

As density of VLSI devices continues to increase at a rapid rate, extensive efforts are being made in development of fine pitch wirebond for IC packages to utilize higher U0 bonds required for recent fme pitch wirebond applications, the effect of the probe mark under the wirebond ball is counts while shrinking chip sizes. With the small size of ball

Novel Low Cost Bumping Process with Non-strip Type Photosensitive Resin and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining

Fine pitch interconnect is one of key technology elements for 2.5D and 3D IC. Low cost and flexibility in technical aspects are also important, so that the technology can be used for wide range of applications. We have newly developed a non-strip type photosensitive resin and propose a novel IMS bumping process with it for finer pitch flip chip joining in a further cost-effective way. The photosensitive resin layer can be used for IMS bumping Mask and Underfill, and we named the resin layer a Mask and Underfill co-usable layer (MU layer). With this technology, several UBM fabrication methods can be chosen. One of options is electro-less plating after MU layer patterning, and in this case, both solder volume and UBM thickness can be designed flexibly without increasing a risk of UBM bridging as well as solder bridging. In this paper, we present detail results on bumping, bonding, reliability tests with this technology with the MU layer for 80 mm pitch test vehicles. Flip chip joining and temperature cycling reliability were demonstrated with electro-less plated Ni/Au UBM. In addition, we have confirmed that the technology is applicable to 40 μm pitch flip chip joints.

Evaluation of back end of line structures underneath wirebond pads in ultra low-k device

Mechanical integrity of back end of line structures underneath wirebond pads was evaluated using 32 nm ultra low-k device by wire pull testing and 3D finite element analysis. Pad tearout rate at wire pull testing was measured for various Cu line/via structures. One key factor for robust bond pads is effective modulus in ULK levels. In addition, increased via and wiring metal density reduces the risk of pad tearout. For the evaluated structures in this work, a calculated effective modulus in ULK was a better index than metal layout type for assessment of bond pad robustness in cooperation with finite element analysis data. Wirebonding is another key factor affecting pad tearout. In this work, effects of wirebond geometry (i.e. wire size and bond ball size) on pad tearout were focused rather than the effect of parameter itself. With the robust BEOL stack and appropriate wirebonding conditions, module level reliability of 35 μm ultra fine pitch wirebond on ultra low-k chip with circuit underneath bond pads was also demonstrated with a PBGA package.

Selective nickel and gold plating for enhanced wire bonding technology

Nickel and gold are electrodeposited on wire bond pads by a newly developed selective plating process in which plating is done without photoresist. The gold terminal metal offers exciting advantage over the traditional aluminum metallurgy. The unique self-encapsulating structure of gold and nickel over copper seed is illustrated. The plating tool, process control and thickness uniformity are described. We have evaluated this structure with probing, aging and stress under high temperature (200degC) in conjunction with bonding. We also varied the bonding conditions to allow a wider choice of inter-level dielectrics and structure/device placement under pads. All the data shows that this is a viable alternative to the current process of record

Manufacturability and reliability of different size wirebonds on different Al pad structures

The manufacturability and reliability of wirebonds depends on many factors, most of which are linked to the BEOL wafer fabrication process. This paper presents a detailed experimental analysis of the effect of pad thickness and liner levels on the quality of the interconnection. Varying ball sizes are evaluated and compared for different target pitch applications. Thermal aging of the wirebonds with subsequent wire pull and ball shear was studied and the challenges of this test are described.

Implementation challenges for scalable neuromorphic computing

In the big data era, a new computing system, called Cognitive Computing, that can handle unstructured data, learn and extract the insights is required. A neuromorphic device is a key component for this, and several architectures are reported. Compared to the neuromorphic device with SRAM-based spiking neural network, a cross-bar structure device realizes on-chip leaning, but requires high-density off-chip interconnect, much higher than those for conventional high-end logic devices. Recent progress of solder bumping and 3-dimentional integration technologies are described.

Flip chip joining with low temperature solders and thermal gradient bonding

In this study, we investigated effects of thermal gradient of joint during flip chip bonding on intermetallic compound (IMC) growth for several solder materials. Cu/Sn-2.5Ag/Cu joint was prepared by bonding electroplated Cu/Sn-2.5Ag bump on Cu pad. Ni/Sn/Ni, Ni/In/Ni, Ni/In-48Sn/Ni, and Ni/Sn-58Bi/Ni joints were prepared by solder capping by IMS on electro-less plated Ni/Au post and bonding it on electro-less plated Ni/Au pad. Joint pitch and diameter were 80 micron and 38 micron respectively. Joints prepared by thermal gradient bonding (TGB) were compared with those by homogeneous temperature bonding (HTB). With Cu/Sn-2.5Ag/Cu joints, firstly we confirmed faster growth of IMCs at a cold end than a hot end of the joint and thicker IMC in the TGB joint than in the HTB joint. These important features of TGB were also confirmed experimentally on joints with low temperature solder materials. It indicates that TGB can be used for the joints with low temperature solders to shorten bonding time for full IMC joint. IMC growth at the cold end of Ni/In/Ni joint prepared by TGB was as fast as that of Ni/Sn/Ni joint by HTB.

Optoelectronic Chip Assembly Process of Optical MCM

Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle intermetallic compounds such as AuSn4 is observed by an energy-dispersive X-ray analysis, and as a result the temperature and the dwell time for the chip assembly process should minimized. Furthermore, if OE chips are underfilled, resin could infiltrate into the total internal reflection mirror cavity, and it will not reflect anymore. On the other hand, Au - SAC joints are not mechanically stable without underfill because of a large thermal stress from the coefficient of thermal expansion mismatch between the OE chip and the optical waveguide-integrated organic substrate. The issue is solved by using sidefill encapsulation instead of underfill. Appropriate material selection of a high viscosity and high thixotropic index prevented infiltration under the chip. The effect of the sidefill process is verified by simulation and experimental results. The chip assembly with sidefill passes more than 1500 deep thermal cycles from -55 °C to 125 °C.

Effects of solder wettability of resist materials on solder filling with Injection Molded Solder (IMS) technology

Injection Molded Solder (IMS) is an advanced solder bumping technology that the solder bumps can be made by injected pure molten solder through the masks. In this study, we investigated effects of solder wettability of resist mask on solder filling performance by solder flow simulation with computational fluid dynamics (CFD) software and experiments with IMS technology. It was confirmed by the simulation that more solder was injected into opening of resist mask with lower contact angle. To vary solder wettability of resist mask experimentally, a metal (Sn) was deposited on patterned resist surface including sidewall of resist openings. Solder wettability measurements and solder filling evaluations were performed. Dynamic contact angle measurements showed improved solder wettability of Sn deposited resist mask with an appropriate substrate temperature control compared with no metal deposited resist mask. It was confirmed that solder filling was improved with the metal deposition and the optimized IMS temperature profile. Improvement of solder wettability of resist mask can widen IMS process window in terms of injection pressure and it is important especially for finer pitch application where higher injection pressure is required.

Mechanical properties of Sn-58Bi, In-3Ag and SAC305 solders measured with fine diameter specimens

Lead-free solders such as SnAg or SnAgCu is widely used for flip chip joining. As a result of higher melting temperature and higher elastic modulus of the lead-free solders compared to eutectic SnPb solder, defect of crack or damage in low-k dielectric layers under bond pad for flip chip joining in the semiconductor chip became a serious issue. The crack or damage is caused by mismatch of coefficient of thermal expansion (CTE) between chip and chip carrier substrate after chip join reflow. Various low melting temperature solders have been investigated and proposed as alternatives to SnAg or SnAgCu solders. Mechanical properties including creep properties are important factors as well as melting temperature for stress relief in micro joints and low-k layers. In this paper, the authors report measurement results of creep properties with fine-diameter-specimens (0.5 mm in diameter) of two low melting temperature solders (Sn-58Bi and In-3Ag) and conventional lead-free solder (Sn-3.0Ag-0.5Cu). The measurement matrix consists of four different strain rates and three different temperatures. The stress component n and the constant A in Nortons creep law were derived for each solder alloy.