Toyohiro Aoki

IMC bonding for 3D interconnection

We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.

Through silicon via process for effective multi-wafer integration

We propose a novel 3D integration method, called Vertical integration after Stacking (ViaS) process. The process enables 3D integration at significantly low cost, since it eliminates costly processing steps such as chemical vapor deposition used to form inorganic insulator layers and Cu plating used for via filling of vertical conductors. Furthermore, the technique does not require chemical-mechanical polishing (CMP) nor temporary bonding to handle thin wafers. The integration technique consists of forming through silicon via (TSV) holes in pre-multi-stacked wafers (> 2 wafers) which have no initial vertical electrical interconnections, followed by insulation of holes by polymer coating and via filling by molten metal injection. In the technique, multiple wafers are etched at once to form TSV holes followed by coating of the holes by conformal thin polymer layers. Finally the holes are filled by using molten metal injection so that a formation of interlayer connections of arbitrary choice is possible. In this paper, we demonstrate 3-chip-stacked test vehicle with 50 × 50 μm-square TSVs assembled by using this technique.

Energy-Efficient 1060-nm Optical Link Operating up to 28 Gb/s

An analysis of a 1060-nm VCSEL with a threshold voltage as low as 1.25 V and 3 dB frequency above 19 GHz in the 2.5 to 5 mA bias current range is presented. An optical link based on a custom-made 90-nm CMOS driver, low power VCSEL and 32-μm diameter photodiode is built and characterized. A 5.2 dB link margin is obtained with a 0.99 mW optical modulation amplitude and an 8.2 dB extinction ratio at 28 Gb/s. A 1.1 pJ/b transmitter power consumption is measured at 26 Gb/s. The platform that we use in the present study would be compatible with a wavelength division multiplexing scheme to reach high aggregate bitrate and channel density with low voltage, power and heat dissipation in a future optical module. Results clearly demonstrate the potential of VCSEL-based links to meet the requirements of next-generation exascale computers and data center systems.

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Youngs modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.

Characterization of micro bump formed by Injection Molded Solder (IMS) technology

Injection Molded Solder (IMS) is an advanced solder bumping technology that the solder bumps can be made by injected pure molten solder through the masks. In this study, 3 different sizes of bumps were fabricated by IMS with PI film mask. 3 different solder types, Sn-Ag-Cu, Sn-Bi, and In-Sn were selected for this study. Firstly, effects of IMS stage temperature on bump mechanical integrity for Sn-Ag-Cu were evaluated by bump shear and cross-sectional IMC observation. It was found that higher temperature produced scalloped Cu6Sn5 IMC at the interface, however lower temperatures produced planar Cu6Sn5 IMC. The bumps fabricated with a lower temperature were subjected to thermal aging, and characterized by shear test and cross-sectional IMC observation. No interfacial failure was observed before and after aging, and shear fracture modes for all bumps were ductile. In addition, lower melting point solders Sn-Bi and In-Sn were subjected to aging, and no interfacial failure was found. Changes in shear strength after aging are dependent on the microstructure at the shear height.

Solder Injected through Via for Multi Stacked Wafers

Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal diffusion through the polymer into a silicon device by using various simple test specimens. It is found that although tin and indium showed some diffusion in the polymer materials, gold, silver, and bismuth showed little diffusion after excess annealing. We conclude that various popular solders such as SnAg, SnBi, and SnIn can be adopted as the solder via material with low risk of metal contamination in silicon.

Novel Low Cost Bumping Process with Non-strip Type Photosensitive Resin and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining

Fine pitch interconnect is one of key technology elements for 2.5D and 3D IC. Low cost and flexibility in technical aspects are also important, so that the technology can be used for wide range of applications. We have newly developed a non-strip type photosensitive resin and propose a novel IMS bumping process with it for finer pitch flip chip joining in a further cost-effective way. The photosensitive resin layer can be used for IMS bumping Mask and Underfill, and we named the resin layer a Mask and Underfill co-usable layer (MU layer). With this technology, several UBM fabrication methods can be chosen. One of options is electro-less plating after MU layer patterning, and in this case, both solder volume and UBM thickness can be designed flexibly without increasing a risk of UBM bridging as well as solder bridging. In this paper, we present detail results on bumping, bonding, reliability tests with this technology with the MU layer for 80 mm pitch test vehicles. Flip chip joining and temperature cycling reliability were demonstrated with electro-less plated Ni/Au UBM. In addition, we have confirmed that the technology is applicable to 40 μm pitch flip chip joints.

Evaluation of back end of line structures underneath wirebond pads in ultra low-k device

Mechanical integrity of back end of line structures underneath wirebond pads was evaluated using 32 nm ultra low-k device by wire pull testing and 3D finite element analysis. Pad tearout rate at wire pull testing was measured for various Cu line/via structures. One key factor for robust bond pads is effective modulus in ULK levels. In addition, increased via and wiring metal density reduces the risk of pad tearout. For the evaluated structures in this work, a calculated effective modulus in ULK was a better index than metal layout type for assessment of bond pad robustness in cooperation with finite element analysis data. Wirebonding is another key factor affecting pad tearout. In this work, effects of wirebond geometry (i.e. wire size and bond ball size) on pad tearout were focused rather than the effect of parameter itself. With the robust BEOL stack and appropriate wirebonding conditions, module level reliability of 35 μm ultra fine pitch wirebond on ultra low-k chip with circuit underneath bond pads was also demonstrated with a PBGA package.

Manufacturability and reliability of different size wirebonds on different Al pad structures

The manufacturability and reliability of wirebonds depends on many factors, most of which are linked to the BEOL wafer fabrication process. This paper presents a detailed experimental analysis of the effect of pad thickness and liner levels on the quality of the interconnection. Varying ball sizes are evaluated and compared for different target pitch applications. Thermal aging of the wirebonds with subsequent wire pull and ball shear was studied and the challenges of this test are described.

Implementation challenges for scalable neuromorphic computing

In the big data era, a new computing system, called Cognitive Computing, that can handle unstructured data, learn and extract the insights is required. A neuromorphic device is a key component for this, and several architectures are reported. Compared to the neuromorphic device with SRAM-based spiking neural network, a cross-bar structure device realizes on-chip leaning, but requires high-density off-chip interconnect, much higher than those for conventional high-end logic devices. Recent progress of solder bumping and 3-dimentional integration technologies are described.