Takashi Imagawa

Coarse-grained dynamically reconfigurable architecture with flexible reliability

This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis

This paper proposes a method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment. Irradiation tests also show the correlation between the number of sensitive bits and the mean time to failure. Furthermore, the temporal error rate of an example application due to soft errors in the datapath were measured and demonstrated for reliability-aware mapping.

High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA

In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.

Image smoothing using spatial iterative methods based on accelerated iterative shrinkage

In recent years, much research interest has developed in image smoothing techniques. With increasing application in various fields, there is a motivation to explore various modes of algorithm implementation of image smoothing. Recently, edge-aware image smoothing techniques have been developed based on fast Fourier transformation methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using spatial iterative methods. The motivation of this is to create a performance baseline using spatial iterative methods such as multigrid (MG), conjugate gradient (CG), and preconditioned conjugate gradient (PCG) methods, for the purpose that the algorithm can be easily adapted to parallel computing systems. We also determine the competitiveness compared with FFT implementation in terms of computational cost. From experimental results, multigrid preconditioned conjugate gradient (MGCG) method provides superior results both in smoothing quality and computational cost compared to all the spatial iterative methods considered. Furthermore, with relaxed tolerance, it demonstrates lower computational complexity compared with FFT implementation, with similar smoothing results but having minor quality compromise. Hence, MGCG provides a relatively competitive spatial domain alternative to frequency domain solver, FFT. In applications which do not require computation of an exact solution, spatial iterative methods can provide a reasonable computation alternative to FFT implementation as their convergence conditions can easily be altered by the user to fit a specific application, as well as possessing the ease for parallel computing adaptation.

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation

Coarse-grained reconfigurable architectures are promising components in future SoCs. They are advantageous over fine-grained FPGAs in terms of tolerance for Single-Event Upset (SEU) as well as area and energy efficiency because they have much smaller amount of configuration SRAMs. To establish a design methodology for coarse-grained reconfigurable architecture for specific application domain, this paper compares coarse-grained reconfigurable fabrics of different routing architectures and shows that reconfigurable architecture with excessive routing resources is not preferable when SEU-tolerance is more important than circuit area.

Image smoothing in the spatial domain using multigrid conjugate gradient methods based on accelerated iterative shrinkage

Recently, edge preserving image smoothing techniques have been developed based on fast Fourier transformation (FFT) methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using a spatial iterative method, multigrid conjugate gradient (MGCG). In the case of FFT solvers, so-called wraparound error occurs in the image boundary due to the periodicity implied by the discrete Fourier transformation. Since the proposed method utilizes iterative methods in the spatial domain, wraparound error free image smoothing can be archived. Experimental results shows that the proposed method provides superior results compared to an FFT solver in terms of computational cost and smoothing quality.

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design

This paper proposes a mixed-grained reconfigurable architecture consisting of fine-grained and coarse-grained fabrics, each of which can be configured for different levels of reliability depending on the reliability requirement of target applications. Thanks to the fine-grained fabrics, the architecture can accommodate a state machine, which is indispensable for exploiting C-based behavioral synthesis to trade latency with resource usage through multi-step processing using dynamic reconfiguration. In implementing the architecture, the strategy of dynamic reconfiguration, the assignment of configuration storage and the number of implementable states are keys factors that determine the achievable trade-off between used silicon area and latency. We thus split the configuration bits into two classes; state-wise configuration bits and state-invariant configuration bits for minimizing area overhead of configuration bit storage. In addition, through a case study of FFT mapping, we experimentally explore the appropriate number of implementable states.

Soft error resilient VLSI architecture for signal processing

This paper presents a reliability-configurable coarse-grained reconfigurable array for signal processing, which offers flexible reliability to soft error. A notion of cluster is introduced as a basic element of the proposed reconfigurable array, each of which can select one of four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by a cluster of the reconfigurable array. A fault-tolerance evaluation of Viterbi decoder mapped on the proposed reconfigurable array demonstrates that there is a considerable trade-off between reliability and area overhead.