Yukio Mitsuyama

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary flip-flop (FF),” which can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65-nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst-case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post-silicon tuning.

Neutron induced single event multiple transients with voltage scaling and body biasing

This paper presents measurement results of neutron induced SEMT (single event multiple transients). We devise an SEMT measurement circuit and evaluate the dependency of SEMT on supply and body voltages using test chips fabricated in a 65nm CMOS process. Measurement results show that transients can arise simultaneously at adjacent six inverters sharing the same well, and SEMT ratio to all the single event transients reaches 40% at 0.7V with reverse body biasing. We also investigate the correlation between the spatial spreading of SEMT and the distance between sensitive nodes in layout. Furthermore, referring to the occurrence rates of single event single transient (SEST) and single event single upset (SESU), we validate the measured results.

Coarse-grained dynamically reconfigurable architecture with flexible reliability

This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.

Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture

This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instability and illustrate that periodically alternating active cells with resting ones will greatly mitigate the effects of the aging process with a negligible power overhead. The area of circuits that are added for immunity to soft errors and for mitigating aging effects is 29.3% of the proposed reconfigurable device. A fault-tolerance evaluation of a Viterbi decoder mapped on the architecture suggests that there is a considerable tradeoff between reliability and area overhead. Finally, we design and fabricate a test chip that contains a 4 × 8 cluster array in a 65-nm process and demonstrate its immunity to soft errors. Accelerated tests using an alpha particle foil showed that the mean time to failure and failure in time are well characterized with the number of sensitive bits and that our architecture can trade off soft error immunity with the area of implementation.

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits

This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary Flip-Flop” that can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65 nm CMOS process. Measurement results show that the adaptive control can compensate PVT variations and improve energy-efficiency of subthreshold circuits significantly compared to worst-case design and operation with guardbanding.

FeRAM circuit technology for system on a chip

The ferroelectric memory (FeRAM) has a great advantage for system on a chip, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM. To enhance the applicability of FeRAM for embedded reconfigurable hardware, three circuit technologies are discussed in this paper. Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, low-power reconfigurable hardware.

Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

This paper presents measurement results of alpha-particle-induced soft errors and multiple cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 V to 0.3 V. We reveal that the soft error rate (SER) at 0.3 V is eight times higher than SER at 1.0 V, and the ratio of MCUs to the total upsets increases as the supply voltage decreases. The SER and ratio of MCUs with body-biasing are also described. In addition, we investigate an impact of manufacturing variability on the soft error immunity of each memory cell. In our measurement, a distinct influence of manufacturing variability is not observed even in subthreshold region.

Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

In this paper, the soft error rate (SER) induced by neutrons in 65-nm 10T static random access memory (SRAM) is measured over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is around eight times that at 1.0 V. The dependence of multiple cell upsets (MCUs) on the supply voltage and on the distance between well ties is also investigated. The dependence of the MCU rate on the supply voltage between 1.0 and 0.5 V is small and increases as the voltage is reduced below 0.5 V. This is because the effect of another mechanism, such as charge-sharing, becomes larger in the subthreshold region, rather than the parasitic bipolar effect, which is considered the dominant mechanism causing MCUs in SRAM at the nominal supply voltage in our design.

Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration

NBTI degradation proceeds while a negative bias is applied to the gate of PMOS, whereas it recovers while a positive bias is applied. Therefore, PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using the state-of-the-art long term prediction model. Experimental results show that the prediction accuracy of timing degradation due to NBTI effect is heavily dependent on granularity of stress probability consideration in timing analysis.