Kazutoshi Wakabayashi

Global scheduling independent of control dependencies based on condition vectors

The authors present a global scheduling method based on condition vectors. The proposed method exploits global parallelism. The technique can schedule operations independent of control dependencies. It transforms the control structure of the given behavior drastically, while preserving semantics to minimize the number of states in final schedule. The method can parallelize multiple nests of conditional branches and optimize across the boundaries of basic blocks. It can also optimize all possible execution paths. An algorithm is proposed which generates a single finite state machine controller from parallel individual control sequences derived in the global parallelization process. Experimental results prove that the global parallelization is very effective.<<ETX>>

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoCs complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

A resource sharing and control synthesis method for conditional branches

A scheduling/allocation and control synthesis algorithm is presented. The proposed algorithm can achieve good resource sharing and synthesize an efficient control sequence for nested conditional branches as well as for straight-line codes. The condition vector concept is introduced to allow mutual exclusion to be detected among operators, and is used to produce more efficient control sequences. The condition vector concept is concerned with the handling of nested condition branches and can be used for other scheduling methods. Results obtained from several experiments indicate that the proposed algorithms are efficient and effective.<<ETX>>

CyberWorkBench: integrated design environment based on C-based behavior synthesis and verification

This paper presents practical usage of C language based high level synthesis. Initially, our system LSI design flow is introduced. Then, applicable area of this tool flow is explained and various merits are discussed such as enabling concurrent design of hardware and software, high reusability of behavioral descriptions and flexibility and compactness of C synthesis based configurable processor, by using industrial design examples. Some statistical data are shown to demonstrate efficiency of C-based high level synthesis compared with RTL-based design.

Power management techniques for control-flow intensive designs

This paper presents a low-overhead controller-based powermanagement technique that re-specifies control signals to reconfigureexisting multiplexer networks and functional units to minimizeunnecessary activity. We demonstrate that conventional powermanagement techniques may often not be suited to control-flowintensive designs, and provide a comprehensive analysis of thepotential negative effects of power management on circuit delay,glitching activity at control and data path signals, and formationof false combinational cycles. We present techniques to performpower management through controller re-specification while avoidingthe above negative effects, and demonstrate the efficiency ofthe techniques through experiments.

Design Space Exploration Acceleration Through Operation Clustering

This paper presents a clustering method called clustering design space exploration (CDS-ExpA) to accelerate the architectural exploration of behavioral descriptions in C and SystemC. The trade-offs between faster exploration versus optimality of results are investigated. Two variations of CDS-ExpA were developed: CDS-ExpA(min) and CDS-ExpA(max). CDS-ExpA(min) builds the smallest possible clusters while CDS-ExpA(max) builds the largest possible ones, reducing further the design space. Results show that CDS-ExpA(min) and CDS-ExpA(max) explore the design space 90% and 92% faster on average than a previously developed annealer-based exploration, method, at the expense of not finding 36% and 47% of the Pareto optimal designs and finding the smallest design that is 7% and 9% on average, larger, and the fastest design 28% and 32% slower, respectively.

Stream applications on the dynamically reconfigurable processor

Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

Cyber : High Level Synthesis System from Software into ASIC

Recent advances in integrated circuit fabrication technology have led to larger and more complex logic circuits. Thus, it is becoming more important to have powerful synthesis tool in order to reduce the chip design cost. Up to now, logic synthesis systems have been used for designing main-frame computers, workstations and personal computers. Since the size of logic circuit becomes larger, the designers need higher level synthesis tools than the conventional logic synthesis systems.

Divide and conquer high-level synthesis design space exploration

A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for high-level synthesis based on a divide and conquer method called Divide and Conquer Exploration Algorithm (DC-ExpA) is presented. DC-ExpA parses an untimed behavioral description given in C or SystemC and clusters interdependent operations which are in turn explored independently by inserting synthesis directives automatically in the source code. The method then continues by combining the exploration results to obtain only Pareto-optimal designs. This method accelerates the design space exploration considerably and is compared against two previous methods: an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) that shows good optimality at high runtimes, and a pattern matching method called Clustering Design Space Exploration Acceleration (CDS-ExpA) that is fast but suboptimal. Our proposed method is orthogonal to previous exploration methods that focus on the exploration of resource constraints, allocation, binding, and/or scheduling. Our proposed method on contrary sets local synthesis directives that decide upon the overall architectural structure of the design (e.g., mapping certain arrays to memories or registers). Results show that DC-ExpA explores the design space on average 61% faster than ASA-ExpA, obtaining comparable results indicated by several quality indicators, for example, distance to reference Pareto-front, hypervolume, and Pareto dominance. Compared to CDS-ExpA it is 69% slower, but obtains much betters results compared to the same quality indicators.

Adaptive Simulated Annealer for high level synthesis design space exploration

This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adpative Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (CyberWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.