Dawood Alnajjar

Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture

This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instability and illustrate that periodically alternating active cells with resting ones will greatly mitigate the effects of the aging process with a negligible power overhead. The area of circuits that are added for immunity to soft errors and for mitigating aging effects is 29.3% of the proposed reconfigurable device. A fault-tolerance evaluation of a Viterbi decoder mapped on the architecture suggests that there is a considerable tradeoff between reliability and area overhead. Finally, we design and fabricate a test chip that contains a 4 × 8 cluster array in a 65-nm process and demonstrate its immunity to soft errors. Accelerated tests using an alpha particle foil showed that the mean time to failure and failure in time are well characterized with the number of sensitive bits and that our architecture can trade off soft error immunity with the area of implementation.

Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment. Irradiation tests also show the correlation between the number of sensitive bits and the mean time to failure. Furthermore, the temporal error rate of an example application due to soft errors in the datapath were measured and demonstrated for reliability-aware mapping.

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

This paper studies performance and timing failure probability of time-shifted redundant circuits and path-/circuit-replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for the path-replica and circuit-replica, the false negative error probability of the circuit-replica is approximately two orders of magnitude less than that of the path-replica circuits. When attaining a false negative error of zero, the probability of error detection and reexecution in time-shifted redundant circuits is comparable to, or rather smaller than that of the path-replica circuits.

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture

A scheme for avoiding delay faults with slack assessment during standby time is proposed in this paper. The proposed scheme performs path delay testing and checks if the slack is larger than a threshold value using selectable delay embedded in basic elements (BE) on a coarse-grained reconfigurable device. If the slack is smaller than the threshold, a pair of BEs to be replaced, which maximizes the path slack, is identified. Experimental results show that for aging-induced delay degradation a small threshold slack, which is less than 1 ps in a test case, is enough to ensure the delay fault prediction.

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design

This paper proposes a mixed-grained reconfigurable architecture consisting of fine-grained and coarse-grained fabrics, each of which can be configured for different levels of reliability depending on the reliability requirement of target applications. Thanks to the fine-grained fabrics, the architecture can accommodate a state machine, which is indispensable for exploiting C-based behavioral synthesis to trade latency with resource usage through multi-step processing using dynamic reconfiguration. In implementing the architecture, the strategy of dynamic reconfiguration, the assignment of configuration storage and the number of implementable states are keys factors that determine the achievable trade-off between used silicon area and latency. We thus split the configuration bits into two classes; state-wise configuration bits and state-invariant configuration bits for minimizing area overhead of configuration bit storage. In addition, through a case study of FFT mapping, we experimentally explore the appropriate number of implementable states.

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

This paper studies performance and timing failure probability of time-shifted redundant circuits and replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately two orders of magnitude less than that of the replica circuits. When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.

Soft error resilient VLSI architecture for signal processing

This paper presents a reliability-configurable coarse-grained reconfigurable array for signal processing, which offers flexible reliability to soft error. A notion of cluster is introduced as a basic element of the proposed reconfigurable array, each of which can select one of four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by a cluster of the reconfigurable array. A fault-tolerance evaluation of Viterbi decoder mapped on the proposed reconfigurable array demonstrates that there is a considerable trade-off between reliability and area overhead.