Keiichi Higeta

Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm

This paper presents a built-in self-test (BIST) scheme, which consists of a flexible pattern generator and a practical on-macro two-dimensional redundancy analyzer, for GHz embedded SRAMs. In order to meet the system requirements and to detect a wide variety of faults or performance degradation resulting from recent technology advances, the microcode-based pattern generator can generate flexible patterns. A practical new repair algorithm for the Finite State Machine (FSM)-based on-macro redundancy analyzer is also presented. It can be implemented with simple hardware and can show fairly good performance compared with conventional software-based algorithms.

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

High-speed, high-density 4-4.5Mb CMOS cache SRAMs do not have speed comparable to that of a 4.5Mb BiCMOS SRAM. This 4.5Mb CMOS SRAM has access time equivalent to that of a BiCMOS SRAM. Key techniques for achieving this speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.

A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS

A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum standby current is introduced. Previously-reported application of this technique is to limited to static circuits. Here it is applied not only to static circuits, but also to clock-distribution drivers, register files and dynamic circuits in RAM macros. Precise clock-skew control, PLL jitter minimization, and optimized buffer insertion on long wires are carried out in accordance with the critical path analysis.

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, which have been used as cache and control storages in mainframe computers. >

External memory BIST for system-in-package

This paper presents the design and implementation of an external memory built-in self-test (BIST) in system-on-chip (SoC) designed for system-in-package (SiP). We implemented the BIST handshaking with the internal bus in the microcontroller core for the purpose of enabling the BIST to access the CPU address space. This implementation allows to reduce the area overhead of the BIST and vary the test conditions flexibly according to each phase of debugging, reliability evaluation and mass-production test. For testing SDRAM and flash, we also designed a microcode based algorithmic pattern generator with enough loop-counters, an infinite looping function and a multiple command sequence generator. This BIST method was applied to consumer products with the IEEE 1149.1 JTAG TAP controller, and enabled multi-test for mass-production on a burn-in tester

A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster

The key to improving the performance of a single chip processor is to incorporate many varieties of SRAM macros with a word/bit-flexible configuration. To improve the performance even more, a configurable organization technique featuring a leaf cell design is proposed. In applying the technique, the timing design became too critical for the high-performance processor. An automatic timing adjuster is thus proposed to adjust the sense amplifier activation timing automatically in each organization. In addition, a low Vth MOS transistor is applied in order to improve access time. To overcome the increase in current leakage due to a low Vth, a back-bias control circuit is also proposed. These techniques in conjunction with a 0.25 /spl mu/m CMOS process make it possible to achieve a 0.9 ns access, 700 MHz SRAM macro.

A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.

Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71 % and 58 % of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, witch have been used as cache and control storages in mainframe computers

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

The amount of data traffic is increasing year by year as the number of data-rich services like cloud services and streaming services are increasing. The number of switch modules between servers should decrease to lower latency, and several servers in each rack should be connected to one switch module with cables in a data centre. Using copper cables to connect racks is attractive in terms of cost minimization. Thin cables, for example 34 AWG copper cables, make maintenance easy. The cable length should be 5-7m to connect between racks, and 34 AWG 7m cable has 48dB loss, including board trace loss, package loss and so on. So far transceivers over 25Gb/s, equalizing 35-40dB channel loss have been proposed [1-4], with which low-loss cables like 26 AWG have been required. We target a 25Gb/s transceiver equalizing over 50dB channel loss, and adopt a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer. Both improve on the minimum input sensitivity and enable data transmission through a channel with over 50dB loss.