Takashi Shinoda

Soft Error Rate Analysis Model (SERAM) for Dynamic NMOS RAMs

Soft Error Rate Analysis Model (SERAM) for dynamic NMOS RAMs is developed. SERAM simulates the three-dimensional diffusion and collection processes of alpha-particle induced carriers for various incidences. To verify SERAM, the frequency of collected charge in one memory cell and soft error rates of 64 K-bit samples were measured. The simulations were in good agreement with the experiments. Memory cell scaling analysis by SERAM shows that if the cell area scales as (1/K)2, the ratio Qc/Qα decreases as (1/K)β, where K>1, β~0.4 for unsealed voltages, and Qc and Qα are the critical charge and the noise charge, respectively.

Nano size cerium hydroxide slurry for scratch-free CMP process

We report recent progress in a novel cerium hydroxide polishing slurry with particle size of about 5 nm nano size cerium hydroxide (NSC) abrasive. NSC has succeeded in omitting particles over 1 μm, and in reducing scratches to 1/30 of those with calcined ceria slurry. Even though, NSC maintains oxide removal rate similar to conventional ceria. Mixing NSC with the specific additives brought out tunable polishing of SiO2, SiN, and poly-Si.