Takenori Morikawa

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs. >

A 40 GHz f/sub T/ Si bipolar transistor LSI technology

A high-speed Si bipolar transistor with f/sub T/ (cutoff frequency) of 40 GHz using advanced BSA (BSG self-aligned) technology is described. The advanced BSA technology is characterized by graded profiled collector, buried emitter electrode structure, and 0.8- mu m design rule. The advanced BSA technology for further improving the f/sub T/ performance of the sub-100-nm-deep base transistor has been developed by adding these three technologies to the basic BSA technology, in which chemical vapor deposition (CVD)-BSG film is used as a diffusion source to form the intrinsic base and the p/sup +/-link region and as a sidewall spacer between emitter polysilicon and base polysilicon electrodes. The optimized transistor using the advanced BSA technology has exhibited a cutoff frequency of 38 GHz at V/sub CE/ of 1 V, and ECL (emitter coupled logic) gate delay time of 29 ps at I/sub CS/ of 0.3 mA.<<ETX>>

A Si bipolar 28-GHz dynamic frequency divider

A dynamic frequency divider applying the regenerative frequency division principle has been developed. A spiral inductor on the silicon substrate used as a load is characterized, and an improved one-port model with the substrate resistance is discussed. A 1/16 frequency divider was implemented with a silicon bipolar technology with a cutoff frequency of 40 GHz. The operation frequency range was 11.8-28.1 GHz, covering the Ka band (18-26.5 GHz). The inductive load has improved the maximum operation frequency by 7%, compared with a conventional circuit. Complemented with a 21-GHz static frequency divider previously reported by the authors, the whole microwave frequency range up to 26.5 GHz has been completely covered with the silicon bipolar technology. The maximum operation frequency of a silicon MMIC has been extended to the millimeter-wave frequency region for the first time. >

A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor

This paper reports a 2.4 Gb/s optical terminal IC that integrates high-speed analog and digital circuits for future optical networks using 60-GHz f/sub T/ self-aligned silicon-germanium (SiGe)-alloy base bipolar transistors. The selective epitaxial growth (SEG) SiGe base was formed by using cold-wall ultra-high vacuum (UHV)/CVD technology. Boron concentration reduction at the SiGe epitaxial layer/Si-substrate interface by using a new treatment prior to SEG leads to electrical characteristics with less dependence on bias voltage. The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-locked loop (PLL), and a D-type flip-flop (D-F/F)), and a 1:16 demultiplexer (DMUX). An input offset control circuit is included in the AGC amplifier for wide dynamic range. Trench isolation and silicon-on-insulator (SOI) technologies are introduced to reduce crosstalk between the amplifiers and the PLL. Power consumptions are 0.6 W at -5.2 V for the analog part and 0.45 W at -3.3 V for the digital part, which does not include the ECL output buffers.

A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems

A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems integrates a transimpedance preamplifier, a limiting amplifier with a reference voltage generator, and a clock and data recovery (CDR) circuit with a phase-locked loop (PLL). For this IC, phase-comparison automatically adjusts the clock phase to the optimum point for data regeneration in the CDR circuit. The receiver IC uses a SiGe bipolar transistor with 60 GHz cutoff frequency. It operates at 10 Gb/s with 660 mW power consumption at 3.3 V.

A Si bipolar chip set for 10 Gb/s optical receiver

The development of a chip set comprised of analog circuits with a bandwidth exceeding 10 GHz and digital circuits operating at 10 Gb/s are required for a 10-Gb/s direct-detection optical receiver. The best performance to date using Si bipolar technology is a 10-GHz bandwidth preamplifier or a 3.6-GHz bandwidth gain-controllable amplifier. A preamplifier and gain-controllable amplifier with a bandwidth exceeding 10 GHz, and decision circuits operating at 10 Gb/s are achieved by optimized high-speed silicon bipolar circuit blocks, including a dual feedback loop, peaking circuit, and impedance matched buffer to achieve a 11.2-GHz bandwidth with 53-dB Omega transimpedance gain. The gain-controllable amplifier uses a current-dividing gain-control and emitter peaking circuit and has 11.4-GHz bandwidth with 20-dB variable gain.<<ETX>>

A selective epitaxial SiGe/Si planar photodetector for Si-based OEICs

This paper reports, for the first time, a P-i-N SiGe/Si superlattice photodetector with a planar structure for Si-based OEICs (Opto-Electronic Integrated Circuits). To make the planar structure, a novel SiGe/Si selective epitaxial growth technology by a cold wall UHV (Ultra-High-Vacuum)/CVD is newly developed. The P-i-N planar SiGe/Si photodetector exhibits a high external quantum efficiency (/spl eta//sub ext/) of 25%-29% with a low dark current of 0.5 pA//spl mu/m/sup 2/ and responds up to 10 Gbit/s at /spl lambda/=0.98 /spl mu/m.

A 10 Gb/s SiGe bipolar framer/demultiplexer for SDH systems

A 10 Gb/s 1:8 frame detecting demultiplexer requires 50% less accuracy of frame detection timing control. This 10 Gb/s demultiplexer with frame detection is fabricated using a SiGe Bipolar process. The relaxation of the accuracy requirement is achieved by a data shift selection architecture. This IC is constructed by a combination of a data shift selection circuit and a parallel shift register circuit. In this architecture, the most accurate control is required in a counter operating at 5 GHz. The core circuit of the IC dissipates only 1.8 W with -4.5 V supply voltage.

A Si bipolar transistor with f/sub max/ of 40 GHz and its application to a 35 GHz 1/16 dynamic frequency divider

The development of a Si bipolar transistor with f/sub max/ (maximum frequency of oscillation) of 40 GHz by employing a process which independently optimizes the cutoff frequency (f/sub T/) and the base resistance (r/sub b/) is discussed. By using a A-BSA (advanced BSG self-aligned) technology, the resistance of the link region, the intermediate base region between the intrinsic and extrinsic ones, is controlled by the rediffusion from the BSG side wall to the link region. This process does not degrade f/sub T/. As a result, f/sub max/ of 40 GHz and f/sub T/ of 43 GHz are realized simultaneously. Using this transistor of 1/16 dynamic frequency divider that operates up to 35 GHz has been constructed. The application of Si bipolar transistors will extend to the millimeter-wave frequency region.<<ETX>>

A 15.5 GHz bandwidth Si bipolar preamplifier

The authors describe an extremely high performance Si bipolar preamplifier, which has a 15.5-GHz bandwidth with a transimpedance gain of 52 dB Omega . To achieve such high performance, the optimization of feedback parameters in the circuit and the realization of the 46-GHz f/sub max/ (maximum frequency of oscillation) transistor were carried out simultaneously. The circuit consists of gain and buffer stages. Employing a dual-feedback configuration in the gain stage design, the preamplifier has broadband and low-noise characteristics. The measured frequency response of the preamplifier, using the optimized circuit and the improved transistors, is shown.<<ETX>>