Takaya Chiba

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.

5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer

A 5 Gbps to 6.4 Gbps transceiver consists of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO PLLs, and a clock recovery unit. The Tx has a 5-tap pre-emphasis filter, and the Rx has an equalizer with intersymbol interference (ISI) monitor. Monitoring the ISI enables a fine adjustment of the loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx can compensate for a transmission loss of up to 20 dB and 15 dB at 6.4 Gbps, respectively. The areas of the Tx and Rx channels including the PLLs are both 3.92 mm/sup 2/. The transmitter dissipates 150 mW/channel at 6.4 Gbps when compensating for a loss of 20 dB, the receiver 90 mW/channel when compensating for 15 dB loss.

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process

We describe a 16-channel 2.5Gb/s high-speed transceiver that operates off a single supply voltage ranging from 0.8V to 1.3V. We fabricated the transceiver in a 90nm standard CMOS, using CMOS full-swing circuits except for a limited number of speed- and timing-critical circuits that were implemented in reduced-swing circuit topologies. The reduced-swing circuits were the last-stage 2:1 selector of the multiplexer, transmitter output stage, the decision latches, phase interpolators and delay cells in the VCOs. At a supply voltage of 0.8V, the power consumption of 16-channel transceiver is 362mW, i.e., 23mW per transceiver channel.