Kohtaroh Gotoh

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.

Technique for controlling effective Vth in multi-Gbit DRAM sense amplifier

We propose the use of a capacitor couple structure to control the effective threshold voltage (Vth) and its application to Vth fluctuation compensation in flip-flop sense amplifiers for multi-gigabit DRAMs. Our proposed sense amplifier functions correctly at up to a 500 mV fluctuation in Vth for the transistor pair in the latch. It does not require extra charging time in the sensing operation for compensation. In addition, the sense-amplifier speed is independent of the Vth value, so our S/A can also compensate the sensing speed fluctuation. This Vth control method and Vth-compensated sense amplifier opens up the possibility of utilizing transistors with gate lengths of less than 0.1 /spl mu/m, where the Vth variations could not be reduced.

Electrical properties of Au/ and YBa2Cu3O7−x/SrTi1−yNbyO3 diodes

Electrical properties of Au/ and YBa2Cu3O7−x/SrTi1−yNbyO3 heterojunctions were studied by measuring their capacitance‐voltage, current‐voltage, and conductance‐voltage characteristics. The heterostructures were made by depositing Au or YBa2Cu3O7−x films on SrTi1−yNbyO3 substrates. The results of the capacitance‐voltage measurement indicated that there was an interfacial layer having a dielectric constant lower than that of bulk SrTiO3 at the Au/SrTiO3 and YBa2Cu3O7−x/SrTiO3 interfaces. The current‐voltage characteristics of the Au/SrTi1−yNbyO3 diodes with substrate Nb concentrations of 0.05 and 0.005 wt. % matched characteristics normally associated Schottky junctions and had a large ideality factor, n, consistent with the low‐dielectric‐constant interfacial layers. When the carrier concentration of the n‐SrTiO3 substrate was 2×1019 cm−3, the Au and YBa2Cu3O7−x junctions showed interfacial‐layer tunneling characteristics. The YBa2Cu3O7−x junctions exhibited two peaks in their conductance‐voltage relations...

5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking

A 6 ns-latency 12 mW 5 Gb/s bidirectional link for short-haul (<5 m) balanced lines uses an on-chip switched-capacitor hybrid with echo-canceling capability. The clock-recovery circuit, based on a phase interpolator, makes the link tolerant to a 100 ppm difference between the frequencies of the transmit and receive clocks.

A CMOS multi-channel 10Gb/s transceiver

A quad 10Gb/s transceiver in 0.11/spl mu/m CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.

5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer

A 5 Gbps to 6.4 Gbps transceiver consists of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO PLLs, and a clock recovery unit. The Tx has a 5-tap pre-emphasis filter, and the Rx has an equalizer with intersymbol interference (ISI) monitor. Monitoring the ISI enables a fine adjustment of the loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx can compensate for a transmission loss of up to 20 dB and 15 dB at 6.4 Gbps, respectively. The areas of the Tx and Rx channels including the PLLs are both 3.92 mm/sup 2/. The transmitter dissipates 150 mW/channel at 6.4 Gbps when compensating for a loss of 20 dB, the receiver 90 mW/channel when compensating for 15 dB loss.

8-channel array of single-chip SQUIDs connection to Josephson multiplexer

A single-chip superconducting quantum interference device (SQUID) array interfaced to a Josephson multiplexer has been developed. A single-chip SQUID consists of a SQUID sensor and a superconducting feedback circuit. Its output is digital and can be processed with a Josephson digital circuit. The parallel output signal from the SQUID array was time-division multiplexed and summed at a single output cable by a Josephson multiplexer in a cryogenic environment. This method reduces the number of cables required for connection between the SQUID chips and room-temperature electronics. The eight-channel SQUID was tested with a 160-gate Josephson multiplexer. The authors verified the operation of the SQUID array at bias frequencies up to 5 MHz, while the multiplexer was operated at 120 MHz. The measured sensitivity was 1.13*10/sup -5/ Phi /sub 0//(Hz)/sup 1/2/ and the cut-off frequency was 350 Hz.<<ETX>>

Thermal‐noise‐limited performance in single‐chip superconducting quantum interference devices

The single‐chip superconducting quantum interference device (SQUID) we made using niobium Josephson junctions integrates a two‐junction SQUID and a superconducting feedback circuit. The switching probability, its derivative to input flux, and the flux spectral density measured by varying the sinusoidal bias frequency and amplitude agree well with thermal noise theory. The best sensitivity and cutoff frequency were 6.2×10−6 Φ0■√Hz and 1.1 kHz for a bias frequency at 10 MHz. The dynamic range was 2.5×105. These data show the SQUID to be suited to practical biomagnetic application.

Fabrication of Josephson junctions using an Al/Ta/Nb structure for x‐ray detection

We fabricated Josephson junctions using an Al/Ta/Nb structure for x‐ray detection. We selected a Ta layer to be the absorber of quasiparticles generated by incident x rays to the junction because of the long lifetime of quasiparticles and the absorption efficiency for x rays. A Nb layer served not only as a barrier for quasiparticle rejection, but also as a buffer layer for deposition of a body centered cubic Ta layer without heating during deposition. An Al layer acted as not only an overlayer for the formation of the AlOx barrier, but also as a layer for quasiparticle trapping. The Nb/AlOx‐Al/Ta/Nb junction showed excellent current‐voltage characteristics.