Takayuki Ezaki

A 160Gb/s interface design configuration for multichip LSI

The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced. 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance. Both the CPU and memory are fabricated in a 0.15/spl mu/m CMOS technology.

An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage

CMOS image sensors with rolling exposure have come to be widely used, but they cannot avoid the distortion inherent to rolling exposure no matter how much exposure speed improves for capturing a moving target. The need has consequently been felt for global-shutter CMOS image sensors.

Novel Low-Temperature CoC Interconnection Technology for Multichip LSI (MCL)

We developed a novel low-temperature chip on chip (CoC) interconnection technology featuring several thousand micro-solder bumps and a low-temperature process below 180degC. The data transfer rate between chips becomes comparable to a system on chip (SoC) by using this technology. The test chips we used had 1402 indium bumps with a diameter of 30 mum and a pitch of 60 mum. Two chips were bonded to each other while controlling the gap and growth of the intermetallic compounds (IMCs) between the two chips. We confirmed from the results of electrical evaluation that the four-terminal resistance of an indium micro bump was around 7 mOmega and the high open/short yield of micro-bump daisy-chain test element groups (TEGs). We thus successfully demonstrated low-temperature CoC technology featuring a flux-less bonding process with indium bumps. We are confident that these technologies will be indispensable to creating new applications.

Extremely-low-noise CMOS Image Sensor with high saturation capacity

We have developed a flat device structure, which we call “FLAT”, with no isolation grooves/ridges and no Si substrate etching in the imaging area of the CMOS Image Sensor (CIS). We employed this FLAT structure to achieve a 1.12 µm pitch pixel CIS with a 1.25 transistor/pixel architecture and excellent image quality. It uses FLAT transistors(Trs) that generate greatly-reduced 1/f noise, and FLAT isolators (Isos) that increase the saturation capacity (Qs) due to increasing both effective photodiode (PD) area and PD potential under low dark current.

An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure

A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.

Impact of embedded DRAM logic devices on semiconductor manufacturing

We have taken the lead in process development, while recognizing the technical difficulties inherent in system solutions involving embedded memory. We have developed processes that integrate a high-speed logic with a large-scale DRAM, with the aim of giving even further distinctiveness to our solutions. In this way, we have successfully realized high-performance system LSIs. Through doing so, we have also realized wide bandwidths, low power consumption rates, and other unique capabilities. Nevertheless, we do not consider the merging method to be the be-all, end-all solution for realizing all types of system LSIs. Rather, we fully realize the need for selection of the optimal process, and incorporate within our vision package development as based on circuit scale, required capabilities, and total costs.

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

This paper presents a 4K2K 480-fps global-shutter CMOS image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140

224-ke Saturation signal global shutter CMOS image sensor with in-pixel pinned storage and lateral overflow integration capacitor

\mu \text{V}_{\mathrm {rms}}

Observation of Rotating Angle Dependence of Tunneling Spectra in Heavily Doped n-Type Silicon

for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the output image within 0.18%. A chip-on-chip integration process realized a front-illuminated image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.

Four-directional pixel-wise polarization CMOS image sensor using air-gap wire grid on 2.5-μm back-illuminated pixels

The required incorporation of an additional in-pixel retention node for global shutter complementary metal-oxide semiconductor (CMOS) image sensors means that achieving a large saturation signal presents a challenge. This paper reports a 3.875-μm pixel single exposure global shutter CMOS image sensor with an in-pixel pinned storage (PST) and a lateral-overflow integration capacitor (LOFIC), which extends the saturation signal to 224 ke, thereby enabling the saturation signal per unit area to reach 14.9 ke/μm. This pixel can assure a large saturation signal by using a LOFIC for accumulation without degrading the image quality under dark and low illuminance conditions owing to the PST.