Shin Sakai

A wide dynamic range checkered-color CMOS image sensor with IR-Cut RGB and visible-to-near-IR pixels

A single-chip wide dynamic range (DR) CMOS image sensor is demonstrated with good color reproducibility imaging for the visible wave band, as well as a high sensitivity for the wide waveband coverage through visible to near infrared (Near-IR) wavebands. We succeeded in developing a checkered White-RGB (WRGB) CMOS image sensor based on the lateral overflow integration capacitor (LOFIC) architecture with optimized capacitance value for each color pixel according to its sensitivity. Using the RGB pixels with an infrared cut (IR-Cut) filter, good color reproducibility for visible lights up to a high saturation light intensity, as well as a high sensitivity performance for visible to Near-IR wavebands by using the W pixels without IR-Cut filter are obtained. The image sensor is a 1/3.3-inch optical format, 1280H × 480V pixels, 4.2-µm effective pixel pitch with pixels placed along with 45° direction WRGB LOFIC CMOS image sensor. The wide DR property is 102-dB in one exposure.

Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor

In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In this image sensor, the size of the photodiode (PD) is 30.0 μmH x 21.3 μmV in the 32.0 μmH x 32.0 μmV pixel. In the pixel, the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending from the edges of the semicircular regions. To generate an electric field greater than the average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. By using the PD structure, which includes the above mentioned n-layer shape and the PD dopant profile with the condition of three times n-type dopant implantation, we achieved to collect 96 % of the charges generated in the PD at the FD within 10 nsec. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed three key characteristics as follows; the image lag was below the measurement limit, the electron transit time in the PD was less than 10 nsec, and the entire PD region had equivalent sensitivity.

A pixel-shared CMOS image sensor using lateral overflow gate

A lateral overflow integration capacitor (LOFIC) based CMOS image sensor sharing two pixels and without row-select transistors has been developed using a newly added lateral overflow gate which directly connects the photodiode and the LOFIC. A 0.18-µm, 2-Poly 3-Metal CMOS technology with a buried pinned photodiode process was employed for the fabrication of the CMOS image sensor having 1/3.3-inch optical format, 1280^H × 960^V pixels, and RGB Bayer color filter and on-chip micro-lens on each pixel. The fabricated CMOS image sensor exhibits a high conversion gain of 84-µV/e^- and a high full well capacity of 6.9 × 10⁴-e^- in spite of its pixel size of 3.0 × 3.0-µm².

224-ke Saturation signal global shutter CMOS image sensor with in-pixel pinned storage and lateral overflow integration capacitor

The required incorporation of an additional in-pixel retention node for global shutter complementary metal-oxide semiconductor (CMOS) image sensors means that achieving a large saturation signal presents a challenge. This paper reports a 3.875-μm pixel single exposure global shutter CMOS image sensor with an in-pixel pinned storage (PST) and a lateral-overflow integration capacitor (LOFIC), which extends the saturation signal to 224 ke, thereby enabling the saturation signal per unit area to reach 14.9 ke/μm. This pixel can assure a large saturation signal by using a LOFIC for accumulation without degrading the image quality under dark and low illuminance conditions owing to the PST.

Experiment and device simulation for photo-electron overflow characteristics on a pixel-shared CMOS image sensor using lateral overflow gate

A wide dynamic range CMOS image sensor with lateral overflow integration capacitor sharing two pixels by using lateral overflow gate (LO-gate) which directly connect the photodiode and the overflow photoelectron integration capacitor (Cs) has been developed. In this paper, the characteristics of the saturated-photoelectrons overflowing to the floating diffusion (FD) and to the Cs have been discussed through the comparison of the results of experiments and device simulations. It is possible to integrate all the saturated photoelectrons in the Cs without leaking to the shared FD by controlling the voltages of the gate electrodes of the transfer transistor and the LO-gate in the pixel which strong light irradiates. The CMOS image sensor consisting of 1/3.3 inch optical format, 3 μm pixel pitch and 1280(H) × 960(V) pixels was fabricated by a 0.18 μm 2P3M CMOS technology with a buried pinned photodiode process and has achieved 84 μV/e- photo-electric conversion gain, 6.9 × 104 e- full well capacity and 90 dB dynamic range in one exposure.

Pixel Scaling in Complementary Metal Oxide Silicon Image Sensor with Lateral Overflow Integration Capacitor

Two wide dynamic range (DR) complementary metal oxide silicon (CMOS) image sensors (CIS) with lateral overflow integration capacitor (LOFIC) have been developed in order to scale down the pixel size. A checker-pattern CIS has achieved high area-efficiency for the full well capacity (FWC) by introducing the rectangle structure and placing the color-filters and on-chip microlens along the direction at an angle of 45°. A shared two pixels CIS has achieved small pixel pitch by introducing a lateral overflow gate that overflows over-saturated photoelectrons from the photodiode to the LOFIC directly. These CISs were fabricated using the 0.18-µm 2-polycrystalline 3-metal CMOS technology with buried-pinned-photodiode process and achieved the high FWC, low noise, wide DR and high resolution performances. These structures are effective for obtaining the small pixel size with the advantageous characteristics of LOFIC CIS. In this paper, these structures, operation methods and measurement results of these CISs have been discussed.

White–Red–Green–Blue Lateral Overflow Integration Capacitor Complementary Metal–Oxide–Semiconductor Image Sensor with Color-Independent Exposure and Widely-Spectral High Sensitivity

A high sensitivity white–red–green–blue (WRGB) complementary metal–oxide–semiconductor (CMOS) image sensor is proposed with color-independent saturation exposure based on lateral overflow integration capacitor (LOFIC) architecture. In case of conventional WRGB image sensors, the W pixels saturate in lower illuminance than the other pixels due to the same saturation exposure of all pixels. This WRGB LOFIC CMOS image sensor solves this problem by optimizing the size of LOFICs for each pixel color according to its sensitivity. The white (W) pixels have about 2.3 times higher sensitivity than the green (G) pixels and have 102-dB dynamic range (DR). Moreover, W pixels without infrared (IR) cut filter have high sensitivity for luminance through visible light band to near IR wave band. This image sensor realize that good color reproductivity imaging for the visible waveband and high sensitivity imaging for a wide waveband by one image sensor.

A 2.8 µm Pixel-Pitch 55 ke- Full-Well Capacity Global-Shutter Complementary Metal Oxide Semiconductor Image Sensor Using Lateral Overflow Integration Capacitor

In this paper, a global-shutter complementary metal oxide semiconductor (CMOS) image sensor using lateral overflow integration capacitor (LOFIC) in each pixel without trade-offs between full-well capacity (FWC) and dark current and between FWC and pixel size has been demonstrated. Because the FWC is determined only by LOFIC, a photodiode (PD) and storage diffusion capacitor (SD) are designed focusing on achieving low dark current performance especially. A 2.8 µm pixel pitch Bayer-RGB color CMOS image sensor with the pinned diffusion capacitor for the storage node was fabricated and achieved both 83.3 e-/s at the PD and 58.3 e-/s at the SD dark current at 60 °C and about 55 ke- full well capacity. A high resolution performance, a high FWC performance and a low dark current performance were simultaneously achieved in this image sensor.

A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors

In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.

Checkered white-RGB color LOFIC CMOS image sensor

We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1/3.3-inch optical format, 1280^H × 480^V pixels, 4.2-µm effective pixel pitch along with 45° direction was designed and fabricated through 0.18-µm 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image sensor has achieved about 108-µV/ē high conversion gain and about 102-dB dynamic range (DR) performance in one exposure.