Yasuhisa Tochigi

A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous

This paper presents a 400H×256V pixel CMOS image sensor including 128 on-chip memory/pixel with 1Tpixel/s in burst operation without cooling and 780Mpixel/s in continuous operation. To improve the read-out speed from the chip, a noise-reduction circuit in pixel and relay buffers is introduced.

A Statistical Evaluation of Random Telegraph Noise of In-Pixel Source Follower Equivalent Surface and Buried Channel Transistors

Using a large-scale array test circuit, both static characteristics and random telegraph noise (RTN) of in-pixel source follower equivalent transistors of a CMOS image sensor with buried and surface channel transistor structures were statistically evaluated under various current and body bias conditions. The distribution of noise intensities at various operational bias conditions, correlations between RTN amplitude and static characteristics were analyzed. It was found that the RTN amplitude has a positive correlation between the subthreshold swing for both types of transistors.

A prototype high-speed CMOS image sensor with 10,000,000 fps burst-frame rate and 10,000 fps continuous-frame rate

In this paper, a high-speed CMOS image sensor having a new architecture and a new operating principle has been developed. The image sensor achieves both the continuous capturing and the burst capturing by a single chip, and has low power consumption, low heat generation, high sensitivity and high S/N ratio. This image sensor consist of mainly four blocks, two dimensional pixel array of 4-transister CMOS active pixel, analog memory arrays connected with each pixel output line independently to the pixel array, scanning circuits and multiple number of output amplifiers. A prototype image sensor was fabricated using a 0.18μm 2-Poly 3-Metal CMOS technology with the die size of 5550 μmH x 4575 μmV, the pixel size of 48 μmH x 48 μmV, the number of pixels of 72H x 32V, the number of analog memories of 104 memories per pixel and the 6 parallel horizontal output circuits and output amplifiers. The aperture ratio is 35% and the conversion gain is 60 μV/e-(input referred). It has been confirmed that this image sensor achieves 10,000,000 fps during burst capturing mode and 10,000 fps during the continuous capturing mode through the image capture experiments of high speed phenomena such as rotating object and discharge phenomenon.

Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor

In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In this image sensor, the size of the photodiode (PD) is 30.0 μmH x 21.3 μmV in the 32.0 μmH x 32.0 μmV pixel. In the pixel, the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending from the edges of the semicircular regions. To generate an electric field greater than the average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. By using the PD structure, which includes the above mentioned n-layer shape and the PD dopant profile with the condition of three times n-type dopant implantation, we achieved to collect 96 % of the charges generated in the PD at the FD within 10 nsec. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed three key characteristics as follows; the image lag was below the measurement limit, the electron transit time in the PD was less than 10 nsec, and the entire PD region had equivalent sensitivity.

A novel analysis of oxide breakdown based on dynamic observation using ultra-high speed video capturing up to 10,000,000 frames per second

Dynamic visualization results of 100 nm-thick oxide breakdown are demonstrated in this work realized by the ultra-high speed video capturing with a frame rate of up to 10M frame-per-second. The correlation of the time-dependent-dielectric-breakdown failure mode and light emission mode are confirmed.

Ultra-high speed video capturing of time dependent dielectric breakdown of metal-oxide-silicon capacitor up to 10M frame per second

In this paper, the ultra-high speed (UHS) video capturing results of time dependent dielectric breakdown (TDDB) of MOS capacitors using the UHS camera with the maximum frame rate of 10M frame per second (fps) are reported. In order to capture the breakdown, we set a trigger circuit which detects the rapid current increase through the MOS capacitor. Some movies have succeeded to capture the intermittent light emissions on some points of the gate during the breakdown. From the movies taken at 100K to 1M fps, the distribution centers of the light emission time and the period were 10 sec and 30 μsec, respectively. From the movies taken at 10M fps, the light emission time and the period were less than 10 μsec. The random failure mode has higher percentage of single light emissions than that of the wear-out failure mode, indicating a correlation between of the light emission mode and the TDDB failure mode.

A statistical evaluation of low frequency noise of in-pixel source follower-equivalent transistors with various channel types and body bias

Both static and low frequency temporal noise characteristics were statistically evaluated for in-pixel source followerequivalent transistors with various channel types and body bias conditions. The evaluated transistor types were surface channel (SC) and buried channel (BC) transistors with or without isolated wells. The gate width/length of the evaluated transistors was 0.32/0.32 μm/μm and the gate oxide thickness was 7.6 nm. The BC transistors without isolated well exhibit noise distribution having a much lower noise level and a steeper slope compared to the SC transistors. For the BC transistors with isolated wells without body bias, the noise level increased compared to the BC transistors with body bias. It has been confirmed that the amplitude of random telegraph noise has a correlation to subthreshold swing factor (SS) for both BC and SC transistors. The increase of the noise level of BC transistors without body bias is due to the increase of the SS originated from a stronger short channel effect.