Takehiko Toyoda

Fully differential direct conversion receiver for W-CDMA using an active harmonic mixer

A fully differential direct conversion receiver IC for W-CDMA is presented. The receiver IC consists of a complete active portion of a W-CDMA receiving system, such as an LNA, quadrature demodulator, low-pass filter (LPF), and variable gain amplifier (VGA). In order to suppress the DC offset, which is the most important issue in a direct conversion system, an active harmonic mixer is applied to the quadrature demodulator. Furthermore, the receiving system, including an LNA and RF filter, adopts a differential architecture to reduce local signal leakage, which generates DC offset. The performance of the entire receiving system was evaluated and the DC offset in steady state was measured at only 40 mV. Moreover, the DC offset variation in the LNA gain change, which has the largest affect on the receiving performance, was limited to 60 mV, which is less than -10 dB compared to the desired signal strength. It was confirmed by computer simulation that the DC offset variation in the LNA gain change did not degrade the bit error rate (BER) performance at all.

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (analog base-band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (high speed downlink packet access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (digital base-band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (high speed packet access) and GSM/EDGE.

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, lowpass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.

A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter

Since a receiver (RX) and a transmitter (TX) are operated simultaneously in a WCDMA transceiver, noise and intermodulation distortion performances of a low-noise amplifier (LNA) are degraded by a large leakage signal from the TX. The degradation of the distortion due to the large leakage signal from the TX has been reported in some previous works, but to our best knowledge, there are no reports about the degradation of noise figure (NF) in a LNA due to the large leakage signal from the TX. In this paper, a 900-MHz LNA for WCDMA terminal with high tolerance for a leakage signal from the TX is proposed. Suitable designs of an input matching circuit and a trap circuit are adopted to improve the tolerance for the leakage signal from the TX. The LNA using the proposed techniques is fabricated using SiGe-BiCMOS process. The measured degradation of NF due to the leakage signal from the TX is suppressed to only 0.12 dB.

A Triple-Band WCDMA Direct Conversion Receiver IC with Reduced Number of Off-Chip Components and Digital Baseband Control Signals

This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9mm×3.0mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4dBm for small signal input level and that of over +1.9dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3dB for ACS Case-II condition.

A low DC offset direct conversion receiver for W-CDMA with low current consumption

We present evaluation results for DC offset in the direct conversion receiver for W-CDMA with low current consumption. Measured results indicate that steady-state DC offset is suppressed to less than 30mV and transitional variation in DC offset with gain change is limited to around 100mV. The computer simulation revealed that negligible degradation in bit error rate (BER) performance due to the DC offset transition occurs with the proposed receiver.