Naoko Ono

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

The fisrt 77 GHz frequency modulated continuos wave (FMCW) radar transceiver IC with an accurate FMCW signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer that is able to output linear FMCW frequency is applied. Measured radar performances, output spectrum and distance of a target, show the transceiver achieves a fundamental function for radar applications.

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.

A 60-GHz CMOS Receiver with Frequency Synthesizer

A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS

An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.

28mW 10Gbps transmitter for 120GHz ASK transceiver

In this paper, we describe a low-power millimeter-wave amplitude-shift-keying transmitter architecture and its design technique. This architecture adopts a push-push-type oscillator. The load-pull-like design technique for the oscillator enables us to extract large output power with the same power dissipation and to remove the power amplifier from the transmitter. The transmitter is fabricated using a 40nm CMOS technology. The core area is 0.11mm2. The measured carrier frequency is adjusted by the backgate voltages of MOSFETs centering at 122GHz. The maximum output power is +0.1dBm with 28.3mW power dissipation. The on-off ratio is 18.2dB and the maximum modulation speed is more than 10Gbps.

A 60-GHz CMOS power amplifier with Marchand balun-based parallel power combiner

A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.

A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

125 GHz CMOS oscillator controlled by p-type bulk voltage

We present a 125 GHz voltage-controlled oscillator (VCO) with a 3.4% tuning range based on a 65 nm CMOS process. The oscillator is tuned by utilizing the capacitance variation in NMOSFETs which is controlled by using the p-type bulk voltage of the NMOSFETs. The VCO has a simple structure to achieve a small internal loss. The VCO has an oscillation frequency of 124.9 GHz, an output power of -1.6 dBm and a power consumption of 17.0 mW at a drain voltage of 1.0 V and a bulk voltage of 0 V. The tuning range is from 122.0 GHz to 126.3 GHz.