Choudhury A. Rahman

A real time vehicle's license plate recognition system

A smart and simple algorithm is presented for a vehicle license plate recognition system. Based on pattern matching, this algorithm can be applied for real time detection of license plates for collecting data for surveying or for some application specific purposes. The proposed system has been prototyped using C++ and the experimental results have been shown for recognition of Alberta license plates.

Efficient distributed arithmetic based DWT architecture for multimedia applications

This paper presents a novel architecture for 9/ Discrete Wavelet Transform (DWT) based on Distributed Arithmetic (DA). The proposed architecture optimizes the performance by exploiting the computational redundancy. The DWT inner product of coefficient matrix is distributed over the input by careful analysis of input, output and coefficients word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation processing elements in space domain. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. In the proposed architecture reducing the clock frequency by two or the supply voltage and maintaining the same throughput as of other architecture achieve the low power by a factor of four. The proposed architecture is therefore scalable and can operate at high speed / consumes low power and has reduced computational complexity (improvement of 77.6% over filter based and 40.27% over lifted based architectures) as compared to already published 9/7 biorthogonal wavelet architectures.

CAVLC Encoder Design for Real-Time Mobile Video Applications

This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.

UMHexagonS algorithm based motion estimation architecture for H.264/AVC

This paper presents an integer pel variable block motion estimation architecture based on JVT accepted UMHexagonS algorithm for H.264/MPEG-4 part 10 (AVC) encoder. The proposed pipelined architecture is capable of calculating the required 41 motion vectors of various size blocks supported by H.264/AVC within a 16/spl times/16 block in parallel. The architecture can be used for rapid prototyping of motion estimation core using FPGA. The performance analysis shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of /spl plusmn/16 at a clock speed of around 30 MHz.

A quarter pel full search block motion estimation architecture for H.264/AVC

This paper presents a novel quarter pel full search block motion estimation architecture for H.264/AVC encoder. The proposed architecture is capable of calculating all 41 motion vectors required by the various size blocks, supported by H.264/AVC, in parallel. The architecture has been prototyped in Verilog HDL, simulated and synthesized for Xilinx Virtex2 FPGA. The experimental result shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of -3.75 to +4.00 at a clock speed of 120 MHz. The maximum speed of the architecture is around 150 MHz.

A hardware-accelerated framework with IP-blocks for application in MPEG-4

In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.

Event Detection by Spatio-Temporal Indexing of Video Clips

—With the continuous recording of video data in current surveillance systems, it is almost impossible to quickly identify frames where events of interest did occur within a camera scene. This paper presents the concept of Spatio-temporal Indexing, which is a novel video indexing and retrieval technique that can be used for event detection. Spatio-temporal Indexing allows the users to rapidly retrieve the video clips that contain events of interest from a given video library. The proposed indexing technique analyzes the video and stores the Spatio-temporal Indexes that will be further processed to retrieve video clips queried by users. The proposed technique was tested on hours of video recordings. The results obtained provide 99.9% accuracy for event detection and retrieval. The average processing time is 3 seconds to create index for 10 minutes of videousing Intel i5-2400 processor.

Eliminating illumination effects by discrete cosine transform (DCT) coefficients' attenuation and accentuation

In this paper, we proposed a discrete cosine transform (DCT)-based attnuation and accentuation method to remove lighting effects on face images for faciliating face recognition task under varying lighting conditions. In the proposed method, logorithm transform is first used to convert a face image into logarithm domain. Then discrete cosine transform is applied to obtain DCT coefficients. The low-frequency DCT coefficients are attenuated since illumination variations mainly concentrate on the low-frequency band. The high-frequency coefficients are accentuated since when under poor illuminations, the high-frequency features become more important in recognition. The reconstructed log image by inverse DCT of the modified coefficients is used for the final recognition. Experiments are conducted on the Yale B database, the combination of Yale B and Extended Yale B databases and the CMU-PIE database. The proposed method does not require modeling and model fitting steps. It can be directly applied to single face image, without any prior information of 3D shape or light sources.

A novel automated microscopy system for the study of population statistics of parasitic nematode

This paper presents a novel automated microscopy system for the analysis of population statistics of parasitic nematode. This system produces a novel and more accurate quantifiable way to determine the effect of anthelmintic drugs/compounds in C. elegans. The aim of this system is to help biomedical researchers improve diagnosis and screen for novel anthelmintics and undertake drug mode of action studies.

An area reduction scheme for the H.264/AVC CAVLC encoder

This paper presents an approach to reduce the area used for the implementation of look up tables (LUTs) in the H.264/AVC Context-based Adaptive Variable Length Coding (CAVLC) encoder. Replacing the LUTs of the coeff_token by an algorithm that closely follows the codeword features and can be easily implemented with simple computational elements, the proposed scheme shows that an area savings of more than 40% can be achieved with a bit-rate increase of less than 0.8%. The proposed approach is very effective to reduce the area for low bit-rate applications such as mobile video applications which have simple/low to moderate motion characteristics.