Tamotsu Owada

Ultrathin Barrier Formation Using Combination of Manganese Oxide Encapsulation and Self-Aligned Copper Silicon Nitride Barriers for Copper Wiring in Future LSI Interconnects

Combining Mn oxide/Ta encapsulation and a self-aligned CuSiN barrier enhanced reliability of both wiring and dielectrics, reducing wiring resistance by 10%, compared with that of a control sample. The CuSiN barrier effectively concentrated Mn, resulting in a composite barrier consisting of Mn oxide, Mn silicate, and MnSiN forming on top of the Cu wiring. Mn concentration is attributed to the large difference in the standard heat of formation between Mn silicide and Cu silicide. The composite barrier that formed on top of the Cu wiring played a critical role in enhancing the reliabilities by suppressing surface Cu self-diffusion, vacancy diffusion, and Cu ion drift under electrical and thermal stresses. Suppressing the surface self-diffusion, for example, increased electromigration lifetime by a factor of 51. This combination technique has an advantage over a previous self-formation of a Mn oxide barrier in terms of reliabilities since the previous technique cannot form such a composite barrier on top of the Cu wiring.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.

Potential of and issues with multiple-stressor technology in high-performance 45 nm generation devices

In this paper, we describe multiple-stressor technology (MST) for high-performance 45-nm-node devices. The combination of two or more stressors, namely, polygate stressor (PGS)/tensile stress liner (SL) for n-channel field-effect transistor (NFET), and embedded SiGe/compressive SL for p-channel field-effect transistor (PFET), is integrated into complementary metal–oxide–semiconductor (CMOS) process and its potential for device performance enhancement is investigated. Moreover, the issues of MST are also discussed from the viewpoint of variations in device characteristics under an extremely high channel strain, which are not pronounced in the previous technology with its relatively low strains.

Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique

As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Youngs modulus increased by 1.7 times compared with that of thermally cured NCS. We fabricated two-level Cu wirings layers with NCS cured by optimized e-beam cure technique. The e-beam cure dramatically enhanced the lifetime of time-dependent dielectric breakdown (TDDB) of interlayer dielectrics. We also examined the influence of the charge damage to the MOSFETs under e-beam cured NCS layer and confirmed that there was no e-beam charge damage to the Ion-Ioff characteristics and reliability of MOSFETs with the optimized e-beam cure.