Tan Zhang

Flip Chip Assembly of Thinned Silicon Die on Flex Substrates

Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.

Flexible Electronics: Thin Silicon Die on Flexible Substrates

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.

Ultra-thin, flexible electronics

Ultra-thin, flexible electronics are advantageous for integration into biomedical sensors, wearable electronics, multifunction surfaces and low profile applications. Although flexible interconnects have been successfully demonstrated for these applications [1], the embedding of thinned, flexible semiconductor die will greatly enhance the application of this technology. Die thinning, thin multilayer substrates and the elimination of solder joints are required to meet the thickness targets for these applications. A process sequence has been developed to achieve final thicknesses of 35–75µm.

Silicon Carbide High Temperature Operational Amplifier

Development of silicon carbide operational amplifier offers an attractive alternative building block for the replacement of silicon and silicon-on-insulator analog circuits in harsh environment applications. NMOS-based enhancement mode silicon carbide device technology was utilized to demonstrate feasibility of operational amplifiers for use in harsh environment applications. This study reports on the results of characterization of operational amplifiers at room temperature and high temperatures up to 350°C. The development of high temperature packaging techniques enabled assembly of a functional oscillator board tested up to 350°C. A test fixture with high temperature sockets enabling quick swap of operational amplifiers is also discussed as an important tool in high temperature electronics research and development.

Flexible electronic assemblies for space applications

This describes the development and evaluation of advanced technologies for the integration of electronic devices within membrane polymers. Specifically, investigators thinned silicon die, electrically connecting them with circuits on flexible (liquid crystal polymer (LCP) and polyimide (PI)) circuits, using gold thermo-compression flip chip bonding, and embedding them within the material. The influence of temperature and flexure on the electrical behavior of active embedded assemblies was evaluated. In addition, the long-term thermal cycle resistance of the passive daisy chain assemblies was determined within the Mil-Std (-55° to +125°C), extreme low #1 (-125° to +85°C), and extreme low #2 (-125° to +125°C) temperature ranges. The results of these evaluations will be discussed, along with the application of this technology for future NASA missions.

Investigation of Thick Film Technology for High Temperature Applications

For electronics operating at 300°C, thick film technology has been proposed as a suitable interconnection technology to create modules. This work examines the leakage current with constant bias (100V) at 300°C. The leakage current increased significantly within the first few hours of aging. The effect of 300°C aging with dc bias on the adhesion of multilayer thick film test structures was also studied. The aged adhesion was a function of bias polarity. Fracture surface analysis results are presented. Bi in the PtPdAu conductor appears to play a role in both the leakage current and adhesion phenomena observed.

Recent Progress in Thin Film Multichip Packaging for High Temperature Digital Electronics

A thin film material and process technology is being developed and evaluated for high temperature (300°C) digital multichip modules for use in geothermal well instrumentation. The substrate technology selected is AlN to minimize the difference in the coefficient of thermal expansion between the substrate and the SiC digital die. A thin film/plated Ti/Ti:W/Au metallization is used with a plasma enhanced chemical vapor deposited Si3N4 to create multilayer interconnections. Active components are assembled to the interconnect substrate using Au stud bump thermocompression bonding. The Au stud bump maintains a monometallic interface between the substrate Au pad surface and the Au pads on the SiC die. A digital circuit has been built and successfully tested as an initial demonstration.

Investigation of Photo-Imageable Thick Film Metallization on Low Temperature Cofired Ceramics (LTCC) for Improved Packaging Density

With the increasing electronics demand on complexity and functionality, low temperature cofired ceramic (LTCC) shows its advantages for cost efficiency under high volume, multilayer high packaging density, and compatibility of passive components integration. However, compared with thin film technology, the minimum thick film line width and spacing on LTCC is 4mil, which limits the packaging of fine pitch devices. In this study, one of DuPont™ photoimageable thick film gold (Au) conductors has been selected to fabricate on DuPont 951PX substrate, with the patterns as small as 1mil. Surface insulation resistance (SIR) and serpentine resistance patterns with a series of line width and spacing was printed and post fired on LTCC to investigate the capabilities and limits of the feature size. Feature dimensions were measured to compare with the design value. Metal adhesion and stud bump patterns are also included in the test substrate. After initial testing, the substrates are undergoing 300°C aging. Post aging...