L. Del Castillo

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Fabrication and characterization of microinductors for distributed power converters

Inductors play a key role in DC-DC converters, but few options exist for implementing on-chip inductors for highly miniaturized, monolithic power converters. Microinductors constructed by standard microelectronic fabrication techniques with magnetic films as the core material have been investigated during the past 20 years with mixed results. A 13-mm/sup 2/ microinductor based on a spiral geometry and having L = 3.2 /spl mu/H and Q = 1.3 at 1 MHz is reported here. Key issues regarding microinductor design and performance are discussed.

Flexible Electronics: Thin Silicon Die on Flexible Substrates

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.

Ultra-thin, flexible electronics

Ultra-thin, flexible electronics are advantageous for integration into biomedical sensors, wearable electronics, multifunction surfaces and low profile applications. Although flexible interconnects have been successfully demonstrated for these applications [1], the embedding of thinned, flexible semiconductor die will greatly enhance the application of this technology. Die thinning, thin multilayer substrates and the elimination of solder joints are required to meet the thickness targets for these applications. A process sequence has been developed to achieve final thicknesses of 35–75µm.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of 65 nm RF-CMOS on SOI

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

An active membrane phased array radar

We have developed the first membrane-based active phased array in L-band (1.26GHz). The array uses membrane-compatible transmit/receive (T/R) modules (membrane T/R) for each antenna element. We use phase shifters within each T/R module for electronic beam steering. We discuss the T/R module design and integration with the membrane. We also present transmit and receive beam-steering results for the array.

Application of commercial electronics in the motors and actuator systems for Mars surface missions

Commercial-off-the-shelf electronic components (COTS) offer a very low cost and attractive solution for construction of electronic systems for Mars missions, including the actuator electronic systems for the Mars Rovers. One issue with using COTS lies in the difference between their specified operating temperature range (-55/spl deg/C to125/spl deg/C for military components) and the temperatures observed at the surface of Mars (-120/spl deg/C to 20/spl deg/C). To compensate for the difference between these temperatures, most of the electronics are placed in a central warm-electronics-box or WEB. In some cases, such as the distributed control system for the actuators, the electronic assemblies that are to be placed on or near the motors are outside of the central WEB. The experimental search consists of two steps. First, a short functional/non-functional test at -120/spl deg/C is used to identify and narrow down the number of candidate COTS that can work at very cold temperatures. More extensive characterization of the parts that passes the short test is performed to determine the operating margins and estimate the thermal cycle life capability for the COTS parts. Finally, the operating margins of the COTS parts are published as a set of specifications.

Reliability assessment of high temperature electronics and packaging technologies for Venus mission

In this paper, the potentials of the current state-of-the-art electronics and packaging technologies for Venus missions is evaluated and intend to address the survivability and reliability of the selected technologies and develop design-for-reliability guidelines for mission integration.

Extreme Temperature Sensing System for Venus Surface Missions

Previous Venus landers used high temperature pressure vessels with passive thermal protection systems and protected conventional electronics, which limited their surface operation life to 127 minutes. The operating life and science return for future Venus surface missions, however, can significantly be increased through the use of high temperature electronics capable of extending the operating range of electronic systems to Venus surface temperatures (up to 480degC). Toward that end, this paper details the development and evaluation (at 480degC) of a stand-alone, high temperature, battery powered, sensor system, including a multi-sensor interface, multiplexer, signal conditioner, and amplifier, that can directly operate at the extremely high temperatures of the Venus surface. This work employs commercial, high temperature sensors, electronic devices, and packaging materials and leverages their operating margin to realize the aforementioned high temperature sensor system. As a result, the technology could rapidly rise through technology readiness level gates for future NASA missions to Venus.

Aperture-coupled thin-membrane microstrip array antenna for beam scanning application

A microstrip array using an aperture-slot-coupling technique with very thin membranes has been developed at the L-band frequency for a beam scanning application. This technology-demonstration array with 4/spl times/2 elements achieved a relatively wide bandwidth of 100 MHz (8%) and /spl plusmn/45/spl deg/ beam scan. Very narrow coupling slots were used with each having an aspect ratio of 160 (conventional slot aspect ratio is between 10 to 30) for coupling through a very thin membrane (0.05 mm thickness). This thin-membrane aperture-coupling technique allows the array antenna elements to be more easily integrated with transmit/receive amplifier (T/R) and phase shifter modules. The paper addresses only the radiator portion of the array. The array and active components will be presented in a separate paper.