Tao Cheng Lu

Polycrystalline-silicon channel trap induced transient read instability in a 3D NAND flash cell string

Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of 10us or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in “pseudo” charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.

Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String

We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.

A highly punchthrough-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell

A novel bias scheme is proposed for non-volatile memory cells arranged in a virtual-ground array that utilizes hot-carrier injections for program and erase operations. By taking two adjacent cells on the same wordline as a unit, and letting the commonly shared n+ region being floating during program and erase, punchthrough immunity is greatly improved. Program/erase speed, endurance, and retention characteristics are comparable to conventional operations. NBit cell is projected to be workable at sub-40 nm node by such scheme.

A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such device is more scalable and has a larger current drive, it is found that the bit states on the two sides of the ldquocommonrdquo body would interact with each other if the body is too thin. The remote charge effect, the remote punch-through effect, and the suppressed read-through capability are clarified to be the major killing factors. If there is a higher intrinsic-Vt along the cellpsilas channel beyond the active thin-body regions, part of the created memory window will be shadowed. Such interferences would become the worst as these cells are arranged in an array having the common-gate feature.