Taro Osabe

A poly-silicon TFT with a sub-5-nm thick channel for low-power gain cell memory in mobile applications

This work presents a gain-cell solution in which a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random-access memory (RAM). This is made possible by the new transistors 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future.

The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.

Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling

The design and scalability of a nano-electro- mechanical memory (NEMory) cell are investigated via analytical modeling and finite element analysis (FEA) simulation. Proportionate scaling of all the cell dimensions provides for improved storage density together with low operating voltages and fast program/erase times. From FEA simulation, a 75-nm-long aluminum cantilever-beam NEMory cell is expected to have sub-1-ns erase and program times for sub-l-V operation. Because there are practical limits to beam and air-gap thickness scaling, it will be difficult to achieve low-voltage operation for very short beams (Lbeam < 50 nm), unless a beam material with a low Youngs modulus is used. Fracture strain imposes a fundamental limit for beam-length scaling. Thus, a high fracture-strain beam material is desirable to extend NEMory scalability.

Charge-injection length in silicon nanocrystal memory cells

We present the first experimental investigation of the lateral charge-injection length for silicon nanocrystal memory cells programmed with source-side injection (SSI). Charge-pumping measurements reveal that the injection length of SSI programming is reducible to 24 nm and suggest the possibility of scaling down the nanocrystal memory for 2-bit/cell operation to the 90-65-nm range of technology nodes.

Engineering variations: towards practical single-electron (few-electron) memory

The origin of device characteristic deviations of a single or a few-electrons memory, which are the most serious obstacles to achieving a practical memory, is studied from the viewpoint of fluctuation of storage dots. Our model, in which dot occupation area is essential for device characteristics, is compared to the measured characteristics of fabricated memory cells with various dot radii and densities. The potential to achieve gigabit class memory is demonstrated. Manufacturing enhancement by isolated-dots storage (MEID) is proposed as the practical benefit of nonvolatile multi-dot memories.

Quantitative Analysis of Random Telegraph Signals as Fluctuations of Threshold Voltages in Scaled Flash Memory Cells

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide

Scaling Limitations for Flexural Beams Used in Electromechanical Devices

Limitations for the miniaturization of flexural beams used in electromechanical devices are examined using the numerical analysis of the Euler-Bernoulli equation. The utilization of structural materials with high strain limit, in conjunction with innovations in processes and structures, will be needed to scale nanoelectromechanical systems beam lengths into the sub-100 nanometer regime.

SESO memory: a CMOS compatible high density embedded memory technology for mobile applications

SESO memory is proposed as a high density, low power embedded memory. Based on an ultra-low leakage thin-film transistor fabricated with standard CMOS logic techniques, this embedded memory has a density almost three times larger than SRAM and requires no additional processing materials. Fabricated SESO transistor characteristics are presented and a 3-transistor cell structure is analyzed, showing SESO memory to be a strong candidate as an inexpensive embedded memory.