Akira Kotabe

The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory

A threshold voltage fluctuation (DeltaVth) due to random telegraph signal (RTS) in a floating-gate (FG) flash memory was investigated. From statistical analysis of the DeltaVth, we found an anomalously large DeltaVth at high percentage region of the DeltaVth distribution, which is caused by a complex RTS. Since the ratio of the complex RTS among the RTS is increased by charge injection to tunnel oxide, the dispersion of the DeltaVth distribution increases after program/erase (P/E) cycle. Since the DeltaVth due to the complex RTS is much larger than the simple RTS, the complex RTS become one of the reliability issues in larger capacity flash memory, especially after P/E cycle

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100muA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.

Doped In-Ge-Te Phase Change Memory Featuring Stable Operation and Good Data Retention

We have fabricated a phase change memory using doped In-Ge-Te to improve the data retention required for industrial and automotive use. This chalcogenide features higher thermal stability as well as denser texture and improved adhesion. The memory cell using doped In-Ge-Te provided a larger read margin and better data retention than conventional Ge2Sb2Tes, and we demonstrated 10-year retention at temperatures above 150degC, which is the highest temperature ever reported.

Quantitative Analysis of Random Telegraph Signals as Fluctuations of Threshold Voltages in Scaled Flash Memory Cells

Random telegraph signals (RTS) in fluctuations of threshold voltage are analyzed using massive readout data in scaled flash memories. A novel quantitative analytical method is proposed to evaluate parameters of the RTS, such as amplitudes and mean time spent in individual states. This evaluation gives us a statistical view of parameters of the RTS as well as their correlations. All of the parameters were found to follow log-normal distribution and to show weak mutual dependences. Possible origins of the distributions are discussed. We also studied evolution of RTS during program/erase operations of flash memories and point out its potential similarity with breakdown phenomena in gate oxide

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.

Low-V t small-offset gated preamplifier for sub-1V gigabit DRAM arrays

A sensing scheme with temporary activation of a low-Vt gated preamplifier (LGA) achieves fast sensing, fast local I/O driving and low-leakage operation simultaneously even for low-voltage mid-point sensing. The features are verified with a 70nm 128Mb DRAM core that demonstrates 16.4ns row access (tRCD) and 14.3ns read access (tAA) at an array voltage of 0.9V. The LGA is promising for future sub-1V gigabit DRAMs because it reduces variation in threshold voltage (Vt) of MOSFETs and in the offset voltage of sense amplifiers.

1-Tbyte/s 1-Gbit DRAM architecture with micro-pipelined 16-DRAM cores, 8-ns cycle array and 16-Gbit/s 3D interconnect for high throughput computing

A novel DRAM architecture with an ultra-high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques: 1) five-stage pipelined 16-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, and 3) a 16-Gbit/s I/O circuit on each of 32 through-silicon-via pairs/DRAM core. We conducted a circuit simulation assuming a 45-nm 1-Gbit chip and confirmed that the proposed architecture achieved a 1-Tbyte/s bandwidth with 19.5-W power consumption.

Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-VT NMOS preamplifier and a cross-coupled high-VT PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-VT CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.