Tatsuya Teshima

Numerical analysis of an anomalous current assisted by locally generated deep traps in pn junctions

An anomalous current observed in reverse-biased pn junctions, highly-integrated with an extremely small cells, is analyzed with the help of device simulation. At the tail of the appearance probability, junction currents showed a steep increase and saturation as a function of applied bias. A model of localized deep-traps is proposed to explain the anomaly. The deep traps are formulated as a g/r center based on the Shockley-Read-Hall model. Simulation results clarify the mechanism of the current anomaly: when deep traps are included in the depletion layer, they act as a carrier generation center and the junction current steeply increases. The magnitude of the current after saturation is discussed, focusing on capture rate and trap density. Further, experimental features for the anomaly, e.g., the fluctuation in the critical voltage at which the current begins to increase and the structure dependence of the anomalous current, are also discussed using the present deep trap model.

High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer

An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.

Normally-off PLED (Planar Localised Electron Device) for non-volatile memory

An advanced Planar Localised Electron Device (PLED) is presented for use as a non-volatile and high-speed random access memory with very low power consumption. A new tunnel barrier configuration is introduced to achieve both write time shorter than 1.0 nsec and retention time over 10 years. An operation scheme based on extremely high ON/OFF current ratios is demonstrated for the first time by conducting numerical simulation of tunnel currents.

High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:/spl Psi/) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO/sub 2/. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO/sub 2//poly-Si/500-nm SiO/sub 2/) wafer. In this device, the highly concentrated p/sup +/ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages.

A Monte Carlo analysis of new nanoscale ballistic field effect transistors (BFETs) for millimetre-wave applications

This paper presents a new nanometre-gate ballistic field effect transistor (BFET) suitable for millimetre-wave applications. The BFET features an inverse modulation-doped channel with a specially designed source contact, enabling maximum use of electron velocity overshoot for the gate length Lg smaller than 100 nm. By performing a self-consistent 2D Monte Carlo simulation that dealt with both intrinsic and extrinsic device regions on an equal footing, we found for the first time that electron preheating in the source contact region enhances /spl Gamma/-L intervalley transitions, significantly decreasing the average electron velocity in the intrinsic region. Based on the numerical results, the general criteria of the source contact structure are clarified to realise BFETs. Excellent BFET scaling properties are demonstrated in comparison with those of HEMTs. The average electron velocity of 20-nm-gate AlGaAs/GaAs BFETs was estimated to be 2.5 times larger than those reported for HEMTs fabricated on GaAs substrates.