Tatsuya Tominari

Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

200 GHz f/sub T/ SiGe HBTs and 80 nm gate CMOS were successfully integrated using the LP-CVD technique for selective SiGe epitaxial growth. Suppressing base resistance enabled us to achieve f/sub MAX/ of 227 GHz, corresponding to f/sub T/ of 201 GHz. Shrunk HBTs of A/sub E/=0.15/spl times/0.7 /spl mu/m/sup 2/ achieved ECL ring oscillator gate delay of 5.3 ps at Ics=1.2 mA. Self-heating effects on junction temperature and device performance were investigated with an emitter-width scaling effect. A low thermal budget HBT process sustains full compatibility with 0.13 /spl mu/m platforms for large scaled RF ICs.

Integration of a 0.13-/spl mu/m CMOS and a high performance self-aligned SiGe HBT featuring low base resistance

Without inducing any degradation of CMOS performance and reliability, a high performance self-aligned SiGe-HBT process was successfully integrated to a standard 0.13-/spl mu/m CMOS platform including dual gate oxides and five layers of Al metallization. Suppressing moisture elimination from a wafer surface is a key for reducing thermal budgets during the SiGe HBT formation process. We found that a heavily boron-doped intrinsic base that is highly activated by 1000/spl deg/C RTA improved HBT performance with low r/sub bb/ of 82 /spl Omega/ and high f/sub T//f/sub max/ of 122/178 GHz.

Ultra-high-speed scaled-down self-aligned SEG SiGe HBTs

A self-aligned selective-epitaxial-growth (SEG) SiGe HBT with a funnel-shape emitter electrode, which is structurally optimized for an emitter being scaled-down towards 100 nm, was developed. This SiGe HBT has an ECL gate delay of 4.9 ps, and implemented in an ultra-high-speed static frequency divider, produces a maximum operating frequency of 81 GHz.

Design of a Reliable p-Channel LDMOS FET With RESURF Technology

High-voltage lateral diffused MOS (LDMOS) FETs have been widely developed and studied for analog application. High-temperature reverse bias (HTRB) instability is one of the largest concerns for this device in achieving high reliability guaranteeing performance stability. This paper focuses on a lower RON approach for 200 V p-channel LDMOS FET with a reduced surface electric field technique, where effectiveness of the drift profile optimization is proposed. Then, HTRB degradation phenomenon relating RON and BVOFF shift was focused on. Through the analysis via device simulation, HTRB shift phenomenon was found to be well simulated with the electron trap feature in the field oxide over the drift region, where the electron was generated by impact ionization under a high-voltage reverse bias stress condition. The technique using a metal field plate for improving impact ionization voltage with maintenance of RON is also proposed for stable p-channel LDMOS FETs that can deliver reliable and high-performance applications.

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.

300 V Field-MOS FETs for HV-switching IC

We have developed 300 V Field-MOS FETs for High-Voltage switching IC. The breakdown voltages are 410 V/370 V with specific on-resistance of 1845/11000 mΩ·mm2 for Field-NMOS/PMOS FETs, respectively. The vertical and lateral electric fields are both optimized to maximize a breakdown voltage at wide range of substrate voltages and minimize a specific on-resistance with a device layout optimization by introducing a Field Pate and a Extended-Drain layer. This technology can apply to 300 V High-Voltage switching IC with a low leak current and a low switching resistance.

Promoting emitter diffusion process and optimization of vertical profiles for high-speed SiGe HBT/BiCMOS

A high-temperature anneal-resistant process, which enables high-speed SiGe HBTs to embed scaled CMOS, is optimized in SiGe BiCMOS technology. This process, called promoting emitter diffusion (PED), is based on enhanced phosphorous diffusion from poly-Si emitter electrodes at high temperature to fabricate thin base layers and shorten the base transit time. By investigating the dependence of high-frequency performance on diffusion temperature, as-grown base layer thickness, and Si cap thickness, the methodology for PED optimization was yielded. In addition, this PED process is effective in reducing an extrinsic base resistance due to deep boron diffusion from poly-Si base electrodes. This indicates that the PED process is very effective at improving the tradeoff relationship between cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ in self-aligned SiGe HBTs using selective epitaxial growth. As a consequence, both f/sub T/ and f/sub max/ of more than 200GHz were successfully obtained.

Design of Novel 300-V Field-MOS FETs With Low on-Resistance for Analog Switch Circuits

Novel 300-V Field-MOS FETs were developed for high-voltage analog switch circuits. The breakdown voltages of the Field-NMOS/PMOS FETs were 410 V/370 V with the specific on-resistance of 1850/11 000 mΩ·mm2 . The vertical and lateral electric fields were both optimized to maximize the breakdown voltage over a wide range of substrate voltages; the device layout optimization included adjusting the silicon-on-insulator thickness and the use of a deep well and a field plate. A low specific on-resistance was obtained as a result of using an extended-drain layer, in addition to the potential linearity of the current pathway in the drift region. This technology can be applied to 300-V analog switch ICs that need to have a low leakage current and a low switching resistance.

A 10V complementary SiGe BiCMOS foundry process for high-speed and high-voltage analog applications

A manufacturable 10V-BVcc/15GHz-fr complementary SiGe BiCMOS foundry process was developed for high-performance multi-media applications. A novel SiGe profile with a forward/backward stepped Ge profile and controllable emitter interface layer improved the SiGe PNPs FOM to 620 GHz ldrV.

Reliability improvement in field-MOS FETs with thick gate oxide for 300-V applications

The reliability of high performance Field-PMOS FET with thick gate oxide was improved. By reducing the amount of charge in the insulating film, RESURF effect was well performed in the drift region to obtain BVDSS over 350 V. Gate oxide breakdown voltage was found to decrease at AC high slew rate, and its reduction was suppressed with the fluorine termination. NBTI shift was also reduced within 15% in a product lifetime. The fluorine termination works as suppressing parasitic charge traps effect in the oxide.