Tomoyuki Miyoshi

Design of a Reliable p-Channel LDMOS FET With RESURF Technology

High-voltage lateral diffused MOS (LDMOS) FETs have been widely developed and studied for analog application. High-temperature reverse bias (HTRB) instability is one of the largest concerns for this device in achieving high reliability guaranteeing performance stability. This paper focuses on a lower RON approach for 200 V p-channel LDMOS FET with a reduced surface electric field technique, where effectiveness of the drift profile optimization is proposed. Then, HTRB degradation phenomenon relating RON and BVOFF shift was focused on. Through the analysis via device simulation, HTRB shift phenomenon was found to be well simulated with the electron trap feature in the field oxide over the drift region, where the electron was generated by impact ionization under a high-voltage reverse bias stress condition. The technique using a metal field plate for improving impact ionization voltage with maintenance of RON is also proposed for stable p-channel LDMOS FETs that can deliver reliable and high-performance applications.

300 V Field-MOS FETs for HV-switching IC

We have developed 300 V Field-MOS FETs for High-Voltage switching IC. The breakdown voltages are 410 V/370 V with specific on-resistance of 1845/11000 mΩ·mm2 for Field-NMOS/PMOS FETs, respectively. The vertical and lateral electric fields are both optimized to maximize a breakdown voltage at wide range of substrate voltages and minimize a specific on-resistance with a device layout optimization by introducing a Field Pate and a Extended-Drain layer. This technology can apply to 300 V High-Voltage switching IC with a low leak current and a low switching resistance.

Design of Novel 300-V Field-MOS FETs With Low on-Resistance for Analog Switch Circuits

Novel 300-V Field-MOS FETs were developed for high-voltage analog switch circuits. The breakdown voltages of the Field-NMOS/PMOS FETs were 410 V/370 V with the specific on-resistance of 1850/11 000 mΩ·mm2 . The vertical and lateral electric fields were both optimized to maximize the breakdown voltage over a wide range of substrate voltages; the device layout optimization included adjusting the silicon-on-insulator thickness and the use of a deep well and a field plate. A low specific on-resistance was obtained as a result of using an extended-drain layer, in addition to the potential linearity of the current pathway in the drift region. This technology can be applied to 300-V analog switch ICs that need to have a low leakage current and a low switching resistance.

Reliability improvement in field-MOS FETs with thick gate oxide for 300-V applications

The reliability of high performance Field-PMOS FET with thick gate oxide was improved. By reducing the amount of charge in the insulating film, RESURF effect was well performed in the drift region to obtain BVDSS over 350 V. Gate oxide breakdown voltage was found to decrease at AC high slew rate, and its reduction was suppressed with the fluorine termination. NBTI shift was also reduced within 15% in a product lifetime. The fluorine termination works as suppressing parasitic charge traps effect in the oxide.

Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS birds beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a products lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

Suppression of self-excited oscillation for common package of Si-IGBT and SiC-MOS

We propose a method to design a module structure avoiding the risk of self-excited (SE) oscillation. By simplifying both the semiconductor device and lumped circuit model, oscillatory conditions can be extracted analytically. Results show good agreement with T-CAD simulation and measurement results of test modules. The method is applied to the design of next generation common package, which has realized very low system inductance. SE oscillation can be prevented for latest generation Si-IGBTs having very small feedback capacitance and SiC-MOS having high output capacitance mounted in the same common package design.

A novel hybrid power module with dual side-gate HiGT and SiC-SBD

In this paper, a novel hybrid power module using a new combination of dual side-gate HiGTs (high-conductivity IGBT) and SiC-SBDs is proposed. This combination achieves drastic switching loss reductions at a turn-off loss of −43%, a turn-on loss of −71%, and a reverse recovery loss of −98% compared with a conventional combination of trench gate HiGTs and U-SFDs (ultra soft & fast recovery diode). As a result, the proposed DuSH module (dual side-gate HiGT hybrid module) has an extremely low inverter loss of −50%, similar to SiC-MOSFETs.

An advanced p-channel LDMOS FET with HTRB tolerability of high-voltage pulse transmitter ICs for ultrasound applications

Novel +/-100-V p-channel LDMOS FET technology were developed for a pulse transmitter IC for an ultrasound application. With a design of steep-profile in drift region for a higher RESURF effect, area efficiency of the output performance can be improved by 20 % of Ron, sp. By an optimization of gate poly-Si structure for reducing electric field and higher tolerability against electron trapping in LOCOS, stable performance against high-temperature reverse bias (HTRB) can be obtained. BVoff/Ron, sp of 260 V/3079 ohm·mm2 of p-channel LDMOS and well matched ID-VDS curve traces between n-channel and p-channel LDMOS FETs enabled the suitable bipolar pulse mirror symmetry with less than -40 dBc of second harmonic distortion in the IC with long-term stability.