Nourhan Bayasi

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm2 area and consumed 2.78-μW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

Adaptive technique for P and T wave delineation in electrocardiogram signals.

The T and P waves of electrocardiogram signals are excellent indicators in the analysis and interpretation of cardiac arrhythmia. As such, the need to address and develop an accurate delineation technique for the detection of these waves is necessary. In this paper, we present a novel robust and adaptive T and P wave delineation method for real-time analysis and nonstandard ECG morphologies. The proposed method is based on ECG signal filtering, value estimation of different fiducial points, applying backward and forward search windows as well as adaptive thresholds. Simulations and evaluations prove the accuracy of the proposed technique in comparison to those proposed techniques in the literature. The mean error for the T peak, T offset, P peak and P offset values are found to be 9.8, 2.3, 7.3 and 3.5 milliseconds, respectively, based on the Physionet QT database, rendering our algorithm as an excellent candidate for ECG signal analysis.

Adaptive ECG interval extraction

ECG intervals such as QRS, QT and PR provide significant information and are widely used as clinical parameters for diagnosing cardiac diseases. This paper presents a novel QRS detection technique based on Curve Length Transform (CLT) and a refined delineation of P-wave and T-wave using Discrete Wavelet Transform (DWT). The proposed technique was verified using the PhysioNet database. The QRS detection achieved a sensitivity of 98.59% and a positive predictivity of 97.86%. The QRS duration, QT interval and PR interval had a mean error of -1.56± 28.8ms, -5.39± 42.4ms and 0.86± 40.3ms respectively. The proposed algorithm is computationally efficient and is simpler to implement in hardware, hence, will lead to a faster execution time, smaller design area and consequently low power consumption.

65-nm ASIC implementation of QRS detector based on Pan and Tompkins algorithm

Electrocardiogram analysis is an important tool in the management of cardiac diseases and the QRS complex is the main reference in such analysis. The paper presents a new adaptive ECG QRS detection ASIC based on Pan and Tompkins algorithm. The algorithm has been modified to detect a large number of different QRS complex morphologies using two adaptive thresholds. The dedicated ASIC design architecture is based on the state-of-the-art 65-nm CMOS technology and has achieved 0.073426 mm2 total core area and 0.55105 μW power consumption. The QRS detector is tested on ECG records obtained from Physionet MIT-BIH database and obtained a sensitivity of Se =99.83% and a positive predictivity of P+= 98.65%.

A 65-nm low power ECG feature extraction system

This paper presents a real-time adaptive ECG detection and delineation algorithm alongside an architecture based on time-domain signal processing of the ECG signal. The algorithm is enhanced to detect large number of different P-QRS-T waveform morphologies using adaptive search windows and adaptive threshold levels. The proposed architecture has been implemented in the state-of-the-art 65-nm CMOS technology. It occupied 0.03416 mm2 area and consumed 0.614 mW power. Furthermore, the non-complex nature of the architecture resulted with a realization using smaller number of computation and higher performance. The design of the QRS detector was tested on ECG records obtained from the Physionet QT database and achieved a sensitivity of Se =99.83% and a positive predictivity of P+= 98.65%. Similarly, the mean error values of the T peak, T offset, P peak and P offset were found to be -1.367, 6.36, 5.5 and -2.59 milliseconds, respectively, using the same database. The small area, low power, and high performance of our architecture makes it suitable for inclusion in System On Chips (SOCs) targeting wearable mobile medical devices.

Self-Powered SoC Platform for Wearable Health Care

This chapter presents a top-level design of the first self-powered SoC platform that can predict, with high accuracy, ventricular arrhythmia before it occurs. The system provides a very high level of integration in a single chip of mainstream modules that are typically needed to build biomedical devices. Hence, the platform could help in reducing the cost in designing not only for ECG monitoring systems, but for generic low-power health care devices. The platform consists of a graphene-based sensors to acquire ECG signals, an analog front-end to amplify and digitize the ECG, a custom processor to perform feature extraction and classification, a wireless transmitter to send the data to a point of care, and an energy harvesting unit to power the whole system. The platform consumes very low power that can be completely powered by the thermal energy generated from the human body. The system is imagined to be integrated within a necklace which can be worn by a patient comfortably. Hence, it can provide a continuous monitoring of the patient’s condition and connect him directly to his doctor for immediate attention if necessary.

Hardware Design and Implementation

The chapter introduces the hardware design of an automated system for prediction and detection of cardiac arrhythmias especially VT/VF. The system’s architecture is presented, the preprocessing stage is explained, then the system control scheme is introduced, and next the specifics for the realization of the QRS complex, the P and T wave signal delineation, and the classification systems are presented. The chapter is concluded by listing the ASIC implementation results of the given system in 65-nm GlobalFoundries process.

System Design and Development

The chapter introduces an automated system for prediction and detection of cardiac arrhythmias especially VT/VF. The system is overviewed, next the ECG signal processing specifics are covered, and then the feature extraction process is explained. The chapter is concluded by explaining features of the classification system.

Performance and Results

The chapter discusses the performance of the presented system. The high-level simulation results are presented, and then a detailed comparison with the published work is given. The chapter is concluded by presenting the obtained results from the first chip tapeout of the introduced system.

The revolution of glucose monitoring methods and systems: A survey

Diabetes is characterized by high glucose levels in the blood that result from defects in insulin secretion, or its action, or both, being considered as one of the major contributors of precipitate infirmity and death in non-contagious diseases. Glucose meter is the prevailing technique to determine the glucose level, a technique involving chemical analysis of a sample of the diabetic blood obtained by pricking a finger. Yet, due to the many demerits of the glucose meter, including the pain and the direct contact requirement, many alternatives were proposed in the literature. In this paper, we explore and compare, based on a number of performance metrics, some of those techniques and systems and their compatibility to be implemented for System-on-Chip (SoC) for glucose and health monitoring, which will potentially transform the future of healthcare by enabling proactive personal health care and ubiquitous monitoring of a patients health profile and condition. A preliminary SoC design for non-invasive glucose monitoring is proposed.