Tero Tikka

WCDMA multicarrier receiver for base-station applications

A multicarrier receiver, which is capable of receiving four parallel WCDMA channels, is described in this paper. The receiver is targeted for base-station applications and designed to drive high-resolution Nyquist-rate A/D converters. The multicarrier receiver achieves 2.6-dB / 3.0-dB NF at the WCDMA channels centered at 2.5 MHz and 7.5 MHz, respectively. The IIP3 for all four WCDMA channels is -12-dBm, and the receiver consumes 535 mW from a 2.5-V supply.

A 1-to-4 channel receiver for WCDMA base-station applications

A base-station receiver, which is capable of receiving from one to four adjacent WCDMA channels, is described in this paper. The receiver is designed to drive high-resolution Nyquist-rate A/D converters and it can be used as a direct-conversion receiver (DCR) or as a low-IF receiver in WCDMA bands I-III. The low-IF NF is 2.7/3.0 dB for the channels centered at 7.5 MHz and 2.5 MHz, respectively. The measured IIP3 of the receiver varies from -10 dBm to -8 dBm depending on the number of the received channels. The power consumption is 542.5 mW from a 2.5-V supply

Multiband receiver for base-station applications

In this paper, a design of an integrated receiver for base-station applications is presented. The receiver is targeted to cover all WCDMA bands and the WiMAX band below 4 GHz. The receiver includes RF front-end, 90-degree phase shifters and programmable baseband filters. The measured voltage gain and NF of the receiver at 2 GHz is 32 dB and 2.6 dB, respectively. The receiver is implemented using a 0.25-mum SiGe BiCMOS process and the power consumption is 432.5 mW from a 2.5 V supply.

CMOS I/Q Subharmonic Mixer for Millimeter-Wave Atmospheric Remote Sensing

A compact second harmonic 180 GHz I/Q balanced resistive mixer is realized in a 32-nm SOI CMOS technology for atmospheric remote sensing applications. The MMIC further includes two on-chip IF amplifiers at the mixers I and Q channels. A conversion gain of +8 dB is achieved with 74 mW of dc power consumption using a 1.2 V supply. The measured IF frequency range is from 1 to 10 GHz. The mixer achieves a 20 dB imagerejection (IR) ratio with an LO input power of +4 dBm. The chip size is 0.75 mm2 including probing pads.

A 1.2 – 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS

This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. As a result, a 17-kHz DCO frequency tuning resolution is demonstrated. Furthermore, implementation details of a low-power programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm2.

Design Aspects of 65-nm CMOS MMICs

We present design aspects and techniques for millimeter-wave circuits implemented in 65-nm CMOS. Different transmission line topologies are discussed and measurement results for a conventional coplanar waveguide and slow-wave coplanar waveguide implemented in 65-nm CMOS are shown. The attenuation of the on-chip transmission lines can be reduced by using slow-wave coplanar waveguides. A 1-stage cascode amplifier in 65-nm CMOS employing inductors as matching elements is presented. On-chip interconnections of the amplifier are implemented and modeled using coplanar waveguides. The ground plane of the coplanar waveguide provides a good ground reference for the entire circuit.

Low-Noise Amplifiers for WCDMA Base-Station Receiver

This paper describes the design and measurements of two different low-noise amplifiers (LNA) targeted for WCDMA base-station applications. The LNAs are designed to have two gain settings, which are optimized for different base-station configurations. Both designs are implemented using the same 0.25 ?m SiGe BiCMOS process, and both designs achieve in high gain mode the NF of 1 dB and IIP3 of -5 dBm.

Design of a high linearity mixer for direct-conversion base-station receiver

The design of a high linearity current-mode mixer, which is targeted for base-station (BS) direct-conversion receiver, is described in this paper. Several different configurations based on the Gilbert cell mixer are compared to achieve a high input referred third-order interception point (IIP3) performance with a low noise figure (NF). According to the simulations the designed mixer achieves +15-dBm IIP3 and 10-dB NF. The mixer draws 7 mA from a 2.5-V supply and has been fabricated with a 0.25-mum SiGe BiCMOS process

Impact of circuit non-idealities on wireless interconnect based on OOK modulated RF transceiver

In this work, a system model for RF wireless interconnect has been proposed based on digital on-off keying (OOK) modulated RF transceiver with 2Gb/s transmission rate and 40GHz carrier frequency. To evaluate performance of wireless interconnect, the impact of critical non-idealities caused by circuit blocks has been analyzed and simulated in Matlab® Simulink® environment. A set of rough circuit specifications and BER performances of such system are obtained, through which key points during actual circuit design has come into view. The result of this work has verified the potential feasibility and reliability, and pointed out possible circuit design stresses for wireless interconnect system.

SiGe BiCMOS High Linearity Mixers for Base-Station Applications

This paper describes design issues related to high linearity SiGe BiCMOS active mixers, which are primarily targeted for WCDMA base-station applications. The effect of different mixer components to overall mixer dynamic range is described, and the measurement results from four different implementations are given to support this discussion. The different mixers are implemented using the same process as part of a complete receiver and thus the interface to baseband filter has been taken into account in the performance analysis. Since one of the goals in the mixer design has been to maximize the mixer bandwidth, the frequency limitations of different alternatives are discussed throughout the paper.