Tetsuji Yasuda

Fixed and trapped charges at oxide–nitride–oxide heterostructure interfaces formed by remote plasma enhanced chemical vapor deposition

This article discusses the preparation of device‐quality oxide–nitride–oxide (ONO) structures by a sequence of low‐temperature plasma‐assisted processes. The emphasis is on the relationship between (i) the chemical bonding (a) within the nitride film and (b) at the internal interfaces of a metal–insulator–semiconductor (MIS) structure, and (ii) the electrical properties of these devices with an ONO gate dielectric. In a MIS device, the flatband voltage is shifted from its ideal value by fixed positive charge primarily at the two internal oxide–nitride (O/N) interfaces. The amount of fixed charge is relatively insensitive to the source gas mixture for nitride deposition, and can be reduced by a rapid thermal annealing (RTA) process. Charge trapping at the SiO2/Si interface is increased by N‐atom migration to this interface that occurs during the nitride deposition, and is more sensitive to the source gas mixture, but also is decreased by a high‐temperature RTA.

Ge metal-insulator-semiconductor structures with Ge3N4 dielectrics by direct nitridation of Ge substrates

We have fabricated Ge metal-insulator-semiconductor structures with ultrathin pure germanium nitride (Ge3N4) films by the direct nitridation of germanium (Ge) substrates. The plasma-enhanced nitridation technique was used with dc plasma source at low temperatures. Capacitance–voltage characteristics with no hysteresis and capacitance equivalent thickness of 1.23 nm have been achieved.

Thin Body III--V-Semiconductor-on-Insulator Metal--Oxide--Semiconductor Field-Effect Transistors on Si Fabricated Using Direct Wafer Bonding

We have demonstrated thin body III–V-semiconductor-on-insulator (III-V-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm2V-1s-1, indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

Coordination and interface analysis of atomic-layer-deposition Al2O3 on Si(001) using energy-loss near-edge structures

The coordination and interface of Al2O3 formed on Si(001) by atomic layer deposition (ALD) were studied using electron energy-loss spectroscopy in a transmission electron microscope. Al energy-loss near-edge structures (ELNESs) were interpreted using first-principles calculations. The Al L23 ELNESs show two peaks at 78.2 and 79.7 eV, which originate from tetrahedrally and octahedrally coordinated aluminum, respectively. The depth profile of coordination in ALD Al2O3/Si was investigated. While both tetrahedrally and octahedrally coordinated Al atoms exist in the ALD Al2O3, the former is dominant near the interface. Aluminum silicate was detected near the interface, and it may cause the difference in aluminum coordination.

Effects of interfacial chemistry on the formation of interfacial layers and faulted defects in ZnSe/GaAs

Existence of Zn‐As and Ga‐Se interfacial layers were suggested by transmission electron microscopy in Zn treated and Se treated or reacted ZnSe/GaAs interfaces, respectively. High densities of As precipitates and Shockley partials were introduced in films with Zn treatment on a c(4×4) As‐rich GaAs surface. In addition, high densities of vacancies and Shockley partials were obtained in samples with a Se‐reacted ZnSe/GaAs interface. Formation of the Shockley partials may originate from the stacking errors induced by disordering of Zn‐ or Ga‐interstitials on the GaAs surface.

III-V-semiconductor-on-insulator n-channel metal-insulator-semiconductor field-effect transistors with buried Al2O3 layers and sulfur passivation: Reduction in carrier scattering at the bottom interface

We have developed III-V-semiconductor-on-insulator (III-V-OI) structures on Si wafers with excellent bottom interfaces between In0.53Ga0.47As-OI channel layers and atomic-layer-deposited Al2O3 (ALD-Al2O3) buried oxides (BOXs). A surface activated bonding process and the sulfur passivation pretreatment have realized the excellent In0.53Ga0.47As-OI/ALD-Al2O3 BOX bottom interface properties. As a result, the III-V-OI n-channel metal-insulator-semiconductor field-effect transistors under the back-gate configuration showed the peak mobility of 1800 cm2/V s and the higher electron mobility than the Si universal one even in the high effective electric field range because of the reduction in the surface roughness and fixed charges.

Pure germanium nitride formation by atomic nitrogen radicals for application to Ge metal-insulator-semiconductor structures

We have investigated the nitridation of germanium using atomic nitrogen radicals generated by a remote rf plasma source. Pure amorphous Ge3N4 films without oxygen are obtained by the direct nitridation of clean Ge substrates. The conformal growth with smooth surface and sharp interface can be achieved in the Ge3N4 films grown at 100°C, where the maximum thickness of the Ge3N4 films is approximately 3nm. While the surfaces of the Ge3N4 films are partially oxidized by the exposure to air, the Ge3N4 films exhibit the high resistance against oxygen diffusion. The Ge3N4 films are water insoluble and soluble in HF. These results demonstrate that pure direct nitridation of Ge substrates has a possibility to be used not only as a passivation layer but also as a diffusion barrier layer against oxygen for Ge metal-insulator-semiconductor field effect transistor applications.

High Electron Mobility Metal–Insulator–Semiconductor Field-Effect Transistors Fabricated on (111)-Oriented InGaAs Channels

Metal–insulator–semiconductor field-effect transistors (MISFETs) were fabricated on the (111)A surface of In0.53Ga0.47As for the first time. Al2O3 gate dielectrics were formed by atomic layer deposition on sulfur-stabilized InGaAs surfaces. The MISFET on (111)A demonstrated channel mobility higher than that on (100), achieving more than 100% improvement with respect to Si even at a high surface carrier concentration.

OPTICAL ANISOTROPY OF SINGULAR AND VICINAL SI-SIO2 INTERFACES AND H-TERMINATED SI SURFACES

We report the first investigation of the optical anisotropy of H‐ and SiO2‐terminated Si surfaces. We examine six different orientations: (110); several vicinal (111); (113); and vicinal (001). Observed reflectance‐difference (RD) spectra fall into two classes according to whether the surface normal is oriented from [111] toward [110] or [001], being consistent with the existence of different step configurations for the two cases. In the (110) class the spectral lineshapes resemble the imaginary part of the Si dielectric function, while in the (001) class they are similar to the energy derivative of the Si reflectance spectrum. To make surface and interface comparison meaningful, we develop an analytic method for correcting interface spectra for the relatively large effects of overlayer thickness. Thickness‐corrected RD spectra of Si–SiO2 interfaces are found to differ in small but distinct ways from those of H‐terminated surfaces of the same orientation, specifically in the enhancement of spectral featur...

Sub-10-nm Extremely Thin Body InGaAs-on-Insulator MOSFETs on Si Wafers With Ultrathin

We have demonstrated sub-10-nm extremely thin body (ETB) InGaAs-on-insulator (InGaAs-OI) nMOSFETs on Si wafers with Al₂O₃ ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding process. We have fabricated the ETB InGaAs-OI nMOSFETs with channel thicknesses of 9 and 3.5 nm. The 9-nm-thick ETB InGaAs-OI n MOSFETs with a doping concentration (N_D) of 10¹⁹ cm^-3 exhibit a peak electron mobility of 912 cm²/V·s and a mobility enhancement factor of 1.7 times against the Si nMOSFET at a surface carrier density (N_s) of 3 ×10¹² cm^-2. In addition, it has been found that, owing to Al₂O₃ UTBOX layers, the double-gate operation improves the cutoff properties. As a result, the highest on-current to the lowest off-current (I_on/I_off) ratio of approximately 10⁷ has been obtained in the 3.5-nm-thick ETB InGaAs-OI nMOSFETs. These results indicate that the high-mobility III-V nMOSFETs can be realized even in sub-10-nm-thick channels.