Tetsuro Itakura

Numerical noise analysis for nonlinear circuits with a periodic large signal excitation including cyclostationary noise sources

A numerical small signal noise analysis method for nonlinear circuits with a periodic large signal excitation, e.g. mixer circuits and switching circuits, is proposed. For small signal input responses, these nonlinear circuits are modeled as their linear periodic time-varying circuits. First, a numerical calculation method for the time-varying transfer function of a linear periodic time-varying circuit is described. Next, a noise analysis method is proposed for these circuits which contain noise sources modeled as cyclostationary random processes. Thermal noise and shot noise in the presence of periodic large signal excitation are modeled as cyclostationary random processes, each of which is modeled as a set of stationary random processes in continuous time. Aliasing components folded back to the baseband from high-frequency bands are calculated, and their powers are accumulated until their contributions become negligible. Simulated noise figures closely matched the measured values. >

A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range

An IF variable gain amplifier with a quadrature demodulator is fabricated using a 0.25-/spl mu/m CMOS technology. An 80-dB linearly controlled gain range is achieved with exponential voltage-to-current converters using MOS transistors biased in a subthreshold exponential region. To avoid the temperature dependence of the gain control characteristic, a master-slave control technique is adopted for the exponential voltage-to-current converters. The experimental results indicate that the proposed technique is effective for a CMOS VGA.

A 19.7 MHz, Fifth-Order Active- RC Chebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme

A fifth-order LPF with a quality factor (Q) tuning circuit has been implemented for draft IEEE802.11n in a 0.13 CMOS technology. The proposed Q tuning technique realizes a low-power 19.7 MHz, active-RC Chebyshev LPF. The filter has dB gain, 30 nV/Hz1/2 input-referred noise, 113 dBmuV input , P 1dB,draws 7.5 mA current from 1.5 V supply, and occupies an area of 0.2 mm2.

Neuro chips with on-chip back-propagation and/or Hebbian learning

A layered neural net realized with two chips is described. One chip implements 24*24 synapses, a local weight control mechanism, and quantized +or-1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given. >

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-P 7-M CMOS technology. The 10-bit, 200-MSPS ADCs achieve DNL of 0.66 LSB, rNL of 1.00 LSB, and SNDR of 54.4 dB that corresponds to 8.7 ENOB. The power dissipation is only 55 mW from a 1.2-V supply.

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.

A 1.9 GHz Si direct conversion receiver IC for QPSK modulation systems

This paper presents a possible BiCMOS solution for a direct conversion receiver (DCR) for QPSK communication systems such as personal handy-phone system (PHS). DCR chips reported are for constant-amplitude modulation systems such as FSK or GMSK. However, no DCR chip for QPSK systems has been reported yet,because a 2nd-order nonlinearity often strongly deteriorates a receiver sensitivity for QPSK systems. That is, amplitude modulation components in QPSK are converted down into spurious baseband signals, while FSK and/or GMSK systems do not suffer from 2nd-order nonlinearity. A DCR chip including an LNA is fabricated for a feasibility study of DCR for QPSK systems.

A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique

This paper presents an area efficient 10-bit, 40 MS/s SAR ADC. The design strategy to minimize the circuit area adopts the pipelined architecture. The 10-bit SAR ADC is divided into 4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage pipelined structure achieves a reduction of the number of capacitors, which is the dominant source of the circuit area of SAR ADCs. To avoid the comparator offset issue, the proposed single-ended 1.5 bit/cycle algorithm is used in the first stage. The single-ended scheme reduces the conversion cycle while maintaining sufficient tolerance of the comparator offset. The second stage uses a pseudo C-2C architecture that is useful for minimizing the load capacitance of the residue amplifier and minimizing the circuit area. Fabricated in 65-nm CMOS with an active area of 0.06 mm2, it achieves a peak SNDR of 55.1 dB and a peak SFDR of 71.5 dB at 40 MS/s sampling rate. The power consumption is 1.21 mW.

All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal

A new digital background calibration technique for gain mismatches and sample-time mismatches in a Time-Interleaved Analog-to-Digital Converter (TI-ADC) is presented to reduce the circuit area. In the proposed technique, the gain mismatches and the sample-time mismatches are calibrated by using pseudo aliasing signals instead of using a bank of adaptive FIR filters which is conventionally utilized. The pseudo aliasing signals are generated and subtracted from an ADC output. A pseudo aliasing generator consists of the Hadamard transform and a fixed FIR filter. In case of a two-channel 10-bit TI-ADC, the proposed technique reduces the requirement for a word length of the FIR filter by about 50% without a look-up table (LUT) compared with the conventional technique. In addition, the proposed technique requires only one FIR filter compared with the bank of adaptive filters which requires (M-1) FIR filters in an M-channel TI-ADC.

A fourth-order bandpass /spl Delta/-/spl Sigma/ modulator using second-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass /spl Delta//spl Sigma/ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-/spl mu/m CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz.