Daisuke Kurose

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-P 7-M CMOS technology. The 10-bit, 200-MSPS ADCs achieve DNL of 0.66 LSB, rNL of 1.00 LSB, and SNDR of 54.4 dB that corresponds to 8.7 ENOB. The power dissipation is only 55 mW from a 1.2-V supply.

A four-input beam-forming downconverter for adaptive antennas

A four-input beam-forming downconverter for adaptive antennas is described. It consists of 2-bit variable gain amplifiers (VGAs), 5-bit local oscillator (LO) signal phase shifters using double RC-bridge circuits, and mixers. The VGAs adjust gain deviation between signal paths. A differential-signal-to-eight-phase-signal converter is employed as a part of the LO phase shifter to reduce the chip size. A maximum phase error of 4.1/spl deg/, which is less than 1/2 LSB, is achieved. This error value indicates that the required phase shifter accuracy and the necessary isolation between the VGAs has been achieved. This beam-forming IC is applicable to receivers with adaptive antennas, and is expected to help to reduce the costs of adaptive antenna systems.

55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers

For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage common-source amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The common-source amplifier with two-stage trnasimpedance gain-boosting amplifiers realizes more than 90 dB. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under the condition, each ADC dissipates only 55 mW.

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the worlds smallest module prototype using the SoC, which is suitable for small mobile devices.

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs

From the viewpoint of a low-power pipeline ADC design, a comparison between two conventional power reduction techniques is discussed. The comparison shows that the amplifier sharing technique has an advantage in terms of the power reduction effect. To confirm the advantage, a test chip of 10-bit 80-MSPS ADC using the amplifier sharing technique is fabricated. The test chip dissipates 55 mW at 80 MSPS (Mega Sample Per Second).

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter

The optimum bit/stage configuration is an important issue in the design of a low-power pipeline analog-to-digital converter (ADC). Prior to this work, power considerations based on a linearmodel have been reported [1]. In this letter, the slew-rate limitation, a non-linear effect, is taken into consideration in low-power design. In the case of a 10-bit, 200-MSPS ADC using 90-nm CMOS technology, the lowest power bit-arrangement was found to be 1.5 bit/stage. A test chip was fabricated for confirmation, and a power dissipation of 105mW was achieved.

A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, the authors employed the I/Q amplifier sharing technique (Kurose, et al., 2005) in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB

A zero-crossing based amplifier whose power is scalable to a sampling frequency is presented. An inverter-based zero-crossing detector (ZCD) is proposed to consume no static power consumption compared with a conventional ZCD using a class-A based preamplifier. A common-mode feedback (CMFB) circuit is adopted to calibrate a variation of a ZCD threshold voltage due to supply voltage and temperature (VT) variations. In addition, the CMFB enables an only single transfer phase for high speed operation. An 11-bit pipelined successive approximation register (SAR) ADC was designed in a 65-nm CMOS technology and a total active area is 0.15 mm2. The post-layout transient noise simulation result shows the signal-to-noise-and-distortion ratio (SNDR) is 60.6 dB at 100 MS/s from a 1.2 V supply voltage. The proposed amplifier consumes 746 uA at 100 MS/s, 376 uA at 50 MS/s and 208 uA at 25 MS/s, respectively.

A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC

This paper presents a power-supply noise canceller (PSNC) for current-steering DAC for high-speed and high-throughput wireless communication systems. Proposed PSNC effectively detects power-supply noise (PSN) and controls the current sources so that PSN would be removed at the output signal. The fabricated 2.24-GHz, 6-bit DAC has demonstrated a maximum of 8.4-dB PSN-reduction. Also, this DAC achieved a spurious-free dynamic-range (SFDR) of larger than 35 dB over full Nyquist frequency.