Tetsutaro Hashimoto

Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement

A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation measurements of VDL. We verified it using an on-die jitter measurement circuit implemented in 90 nm CMOS technology and 0.880 ps timing resolution was obtained experimentally.

A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors

A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9 mm /spl times/ 10.3 mm chip is fabricated in a 90 nm 9M CMOS process and consumes 5 W at 533 MHz.

Supply Voltage Adjustment Technique for Low Power Consumption and Its Application to SOCs with Multiple Threshold Voltage CMOS

An energy-saving system for SOCs using multiple threshold voltage CMOS was developed. It equips process sensors and process-voltage conversion table generated from static timing analysis results, and adjusts. The supply voltage according to die-to-die process variation. We applied this system to an embedded dual-core microprocessor using 90nm triple Threshold voltage CMOS technology. When the microprocessor executes video stream decoding program, 17% power reduction was measured with dies of typical process condition

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications

A real-time on-die noise sensor continuously detects up to 100 noise events per second without disturbing processor operations, using a 400kb/s serial interface. The noise sensor uses histogram counters and variable detection windows. The sensor measures periodic and single-events in real time. The noise sensor is implemented in a 90nm CMOS testchip.

An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive clocking control circuit with SPARC processor cores was fabricated in a 20-nm CMOS process. Experimental measurements demonstrated that the adaptive clocking control circuit achieved the state-of-the-art frequency gain of 7.5%, resulting in the operating frequency as high as 5 GHz.

Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scaling

Low power techniques such as clock gating and dynamic frequency scaling cause a sudden surge in power supply current. To reduce the voltage droop induced by such a surge in the load current of an LDO regulator, we propose output voltage boost and adaptive response scaling techniques that utilize clock activation detection. Measured results from a test chip fabricated in 65-nm CMOS technology show that a combination of the two techniques reduces the worst-case output voltage droop by 63% compared to operation without them. This results in a voltage offset reduction from 45% to 15%, which leads to 20% power savings.