S. Satoh

Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's

Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues remain to be clarified in neutron-induced SE phenomena. This letter reports the geometric effect of multiple-bit SEs induced by neutrons. Multiple-bit SEs in 16 Mb DRAMs are investigated and their geometric effects on high reliability systems are discussed.

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

Simple method for estimating neutron-induced soft error rates based on modified BGR model

Recently the importance of cosmic ray neutron-induced soft errors has been recognized. We propose a simple model to estimate the neutron-induced soft error rates (SERs), which is a modified version of the burst generation rate (BGR) model. Our model can be used to easily and quickly estimate neutron-induced soft error rates and provides a useful guideline for device and circuit engineers to estimate neutron-induced soft errors (SEs),.

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

We numerically studied the neutron effects on submicron CMOS SRAM and LATCH circuits using a developed simulator which agrees well with the experimental charge collection measurements. We showed that the neutron effects have influence on SEs in advanced integrated circuits, especially for LATCH. If the Pb-Sn solder or other materials with high /spl alpha/-particle emission rates are not included, the neutrons are main SE components in advanced integrated circuits.

Cosmic ray neutron-induced soft errors in sub-half micron CMOS circuits

We numerically investigated cosmic ray neutron-induced soft errors in sub-half micron CMOS SRAM and latch circuits at sea level. For our purpose, we developed an original simulator which reproduces well the experimental charge collection data. We investigated soft error rates (SERs) and showed that the neutron-induced SERs in the SRAM are the same order as those due to /spl alpha/-particles and the SERs in the latch are dominated by neutrons.

Neutron-induced soft error simulator and its accurate predictions

We developed the Neutron Induced Soft Error Simulator (NISES) to clarify the role of cosmic ray neutrons in soft errors (SEs). A recently proposed nuclear reaction theory forms the foundation of the nuclear reaction database of the NISES. NISES accurately reproduces the measured neutron-induced charge collection data in SOI diode test structures and the neutron-induced SER data in sub-half micron CMOS circuits. The need for neutron-induced SE simulator like NISES should increase with the recognition of the importance of cosmic ray neutron-induced SEs.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

The authors proposes a characteristic current (I_chr) to replace the conventional saturation drive current used to estimate approximate CMOS inverter delay times for deeply scaled devices. The authors also present a new device design method based on I_chr to achieve a higher operation frequency for CMOS inverter circuits. The new method shortens propagation delay time (Tpd) by 15%

First Quantitative Observation of Local Temperature Fluctuation in Millisecond Annealing

We report, for the first time, a detailed study of the 100 mum-scaled emissivity and temperature variation in millisecond annealing (MSA) depending on the Si trench structure, the shallow trench isolation (STI) structure, and transistor structure measured by Thermawave method. Flash lamp annealing (FLA) was applied as MSA technique. In case of Si trench structure with varying the trench depth, the relation between the trench depth and emissivity was clarified quantitatively. It was found that micro temperature variation within a chip driven by the emissivity variation exceeds of 100degC as the transistor structure was annealed by FLA.