Tetsuya Shimomura

A superscalar RISC processor with pseudo vector processing feature

A novel architectural extension, in which floating-point data are transferred directly from main memory to floating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of 1.2 Gbyte/s, and effective performance reaches 267 MFLOPS (89% of the peak performance) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm/spl times/15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and scoreboard-based dependency check method allow the extension to be realized without affecting the operating frequency.

A one chip super graphics CPU with direct unified memory controller suitable for car information and control system

A one chip super graphics CPU with graphics and unified memory controller has been developed. It requires no dedicated graphics memory and has significantly lower system cost with 1.6 times higher performance than CPUs with state-of-the-art technology. Its process and package are 0.18 /spl mu/m and 256 pin QFP, respectively.